Gate structures for semiconductor devices

1. A semiconductor device, comprising:

a substrate;

first and second pair of epitaxial source/drain (S/D) regions disposed on the substrate;

first and second nanostructured channel regions disposed between the epitaxial S/D regions of the first pair of epitaxial S/D regions and between the epitaxial S/D regions of the second pair of epitaxial S/D regions, respectively; and

first and second gate structures with effective work function values different from each other, wherein the first and second gate structures comprise:

first and second high-K gate dielectric layers surrounding the first and second nanostructured channel regions, respectively;

first and second barrier metal layers with thicknesses different from each other disposed on the first and second high-K gate dielectric layers, respectively;

first and second work function metal (WFM) oxide layers with thicknesses substantially equal to each other disposed on the first and second barrier metal layers, respectively;

a first dipole layer disposed between the first WFM oxide layer and the first barrier metal layer; and

a second dipole layer disposed between the second WFM oxide layer and the second barrier metal layer.

2. The semiconductor device of claim 1 , wherein the first and second barrier metal layers have first and second stacks of layers, respectively;

wherein each layer of the first and second stacks has a thickness substantially equal to each other; and

wherein the second stack has more layers than the first stack.

3. The semiconductor device of claim 1 , wherein the first and second gate structures further comprise first and second barrier metal oxide layers disposed on the first and second barrier metal layers, respectively; and

wherein the first and second barrier metal oxide layers comprise an oxide of a metal in the first and second barrier metal layers, respectively.

4. The semiconductor device of claim 3 , wherein a metal concentration profile across the first WFM oxide layer and the first barrier metal oxide layer has a peak concentration at an interface between the first WFM oxide layer and the first barrier metal oxide layer.

5. The semiconductor device of claim 3 , wherein a nitrogen concentration profile across the first barrier metal layer and the first barrier metal oxide layer has a peak concentration at an interface between the first barrier metal layer and the first barrier metal oxide layer.

6. The semiconductor device of claim 1 , wherein each of the first and second WFM oxide layers comprises an oxide of rare-earth metals or of metals from group IIA, IIIB, or IVB of the periodic table.

7. The semiconductor device of claim 1 , wherein each of the first and second WFM oxide layers comprises an oxide aluminum-based metals or of metals from group IIIA, VA, or VB of the periodic table.

8. The semiconductor device of claim 1 , wherein the first and second dipole layers comprise metal ions of rare-earth metals or of metals from group IIA, IIIB, or IVB of the periodic table.

9. The semiconductor device of claim 1 , wherein the first and second dipole layers comprise metal ions of aluminum-based metals or of metals from group IIIA, VA, or VB of the periodic table.

10. The semiconductor device of claim 1 , wherein the first and second gate structures further comprise third and fourth barrier metal layers disposed on the first and second WFM oxide layers, respectively; and

wherein the first, second, third, and fourth barrier metal layers have a same metallic material.

11. A semiconductor device, comprising:

a substrate;

first and second pair of epitaxial source/drain (S/D) regions disposed on the substrate;

first and second fin regions disposed between the epitaxial S/D regions of the first pair of epitaxial S/D regions and between the epitaxial S/D regions of the second pair of epitaxial S/D regions, respectively; and

first and second gate structures comprising:

first and second high-K gate dielectric layers disposed on the first and second fin regions, respectively;

first and second barrier metal layers with thicknesses different from each other disposed on the first and second high-K gate dielectric layers, respectively;

first and second barrier metal oxide layers disposed on the first and second barrier metal layers, respectively;

an aluminum (Al)-free rare-earth metal-based (REM-based) work function metal (WFM) oxide layer disposed on the first barrier metal oxide layer; and

an Al-based WFM oxide layer disposed on the second barrier metal oxide layer.

12. The semiconductor device of claim 11 , wherein a lanthanum (La) concentration profile across the Al-free REM-based WFM oxide layer and the first barrier metal oxide layer has a peak La concentration at an interface between the Al-free REM-based WFM oxide layer and the first barrier metal oxide layer.

13. The semiconductor device of claim 11 , wherein an Al concentration profile across the Al-based WFM oxide layer and the second barrier metal oxide layer has a peak Al concentration at an interface between the Al-based WFM oxide layer and the second barrier metal oxide layer.

14. The semiconductor device of claim 11 , wherein the Al-free REM-based WFM oxide layer comprises lanthanum oxide.

15. The semiconductor device of claim 11 , wherein the Al-based WFM oxide layer comprises aluminum oxide.

16. The semiconductor device of claim 11 , wherein the first and second gate structures further comprise:

an REM-based dipole layer disposed between the Al-free REM-based WFM oxide layer and the first barrier metal oxide layer; and

an Al-based dipole layer disposed between the Al-based WFM oxide layer and the second barrier metal oxide layer.

17. A method, comprising:

forming first and second nanostructured channel regions in a fin structure on a substrate;

forming first and second high-K gate dielectric layers surrounding the first and second nanostructured channel regions, respectively;

forming first and second barrier metal layers of different thicknesses on the first and second high-K gate dielectric layers;

forming first and second work function metal (WFM) oxide layers of substantially equal thicknesses on the first and second barrier metal layers, respectively;

performing a drive-in anneal process on the first and second WFM oxide layers, wherein performing the drive-in anneal process comprises performing first and second anneal processes that are different from each other;

forming third and fourth barrier metal layers of substantially equal thicknesses on the first and second WFM oxide layers; and

forming first and second gate metal fill layers on the third and fourth barrier metal layers, respectively.

18. The method of claim 17 , wherein the forming the first and second barrier metal layers comprises:

selectively forming a first number of nitride layers on the first high-K gate dielectric layer; and

selectively forming a second number nitride layers on the second high-K gate dielectric layer, wherein the first number is greater than the second number.

19. The method of claim 17 , wherein the forming the first and second barrier metal layers comprises:

depositing a first nitride layer on the first and second high-K gate dielectric layers;

etching a first portion of the first nitride layer that is on the second high-K gate dielectric layer; and

depositing a second nitride layer on the second high-K gate dielectric layer and on a second portion of the first nitride layer that is on the first high-K gate dielectric layer.

20. The method of claim 17 , wherein the performing the drive-in anneal process comprises:

soak annealing the first and second WFM oxide layers at a first temperature between about 550° C. and about 800° C.; and

spike annealing the first and second WFM oxide layers at a second temperature between about 700° C. and about 900° C.