IP Library Granted Patent US 11,025,162
Granted Patent B2
US 11,025,162 · App. 16/836,049 · Granted Jun 1, 2021

Charge pump systems, devices, and methods

Inventors: David Zimlich (Dana Point, CA); Vincent Cheung (San Gabriel, CA)
Assignee: WISPRY, INC.
H02M3/07B81B5/00B81B7/008B81B7/04G05F3/205B81B2203/04B81B2207/053H02M2001/0003
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Quick Facts
Patent No.
US 11,025,162
App. No.
16/836,049
Granted
Jun 1, 2021
Kind
B2
Abstract

The present subject matter relates to charge pump devices, systems, and methods in which a plurality of series-connected charge-pump stages are connected between a supply voltage node and a primary circuit node, and a discharge circuit is connected to the plurality of charge-pump stages, wherein the discharge circuit is configured to selectively remove charge from the primary circuit node.

Claims (42)

1. A controllable power supply comprising:

a plurality of series-connected charge-pump stages connected, at a first end, to a supply voltage node and, at a second end, to a common primary circuit node;

a discharge circuit, comprising a plurality of sub-circuits or circuit elements, the discharge circuit being connected, at a first discharge end, to the common primary circuit node and, at a second discharge end, to a reference, wherein the discharge circuit is configured to selectively remove charge from the common primary circuit node; and

a voltage measurement device configured to measure a present charge state at the common primary circuit node;

wherein the voltage measurement device is connected in communication with one of the plurality of charge-pump stages; and

wherein the voltage measurement device is configured to extrapolate the present charge state at the common primary circuit node from a voltage measurement taken at the one of the plurality of charge-pump stages.

2. The controllable power supply of claim 1 , wherein the discharge circuit is also connected to the plurality of charge-pump stages at a location other than the common primary circuit node.

3. The controllable power supply of claim 1 , wherein each of the charge-pump stages comprises a silicon-on-insulator (SOI) device.

4. The controllable power supply of claim 1 , wherein the discharge circuit comprises:

a plurality of transistors arranged in a cascaded array between the common primary circuit node and the reference, wherein each of the plurality of transistors is connected between two charge pump stages of the plurality of charge pump stages or between a charge pump stage and either the common primary circuit node or the supply voltage node; and

a shorting switch connected between the plurality of transistors and the reference.

5. The controllable power supply of claim 4 , wherein each of the plurality of transistors comprises a silicon-on-insulator (SOI) device.

6. The controllable power supply of claim 4 , wherein the discharge circuit comprises a diode connected between a gate and a drain of each of the plurality of transistors.

7. The controllable power supply of claim 4 , wherein the shorting switch comprises a gate of one of the plurality of transistors that is closest to the reference.

8. The controllable power supply of claim 1 , comprising a clock driver circuit in communication with the series-connected charge-pump stages.

9. A method for regulating charge at a common primary circuit node, the method comprising:

selectively driving charge between stages of a plurality of series-connected charge-pump stages connected, at a first end, to a supply voltage node and, at a second end, to a common primary circuit node;

using a voltage measurement device to measure a present charge state at the common primary circuit node; and

selectively removing charge from the common primary circuit node through a discharge circuit, comprising a plurality of sub-circuits or circuit elements, the discharge circuit being connected, at a first discharge end, to the common primary circuit node and, at a second discharge end, to a reference;

wherein the voltage measurement device is connected in communication with one of the plurality of charge-pump stages; and

wherein the voltage measurement device is configured to extrapolate the present charge state at the common primary circuit node from a voltage measurement taken at the one of the plurality of charge-pump stages.

10. The method of claim 9 , wherein the discharge circuit is also connected to the plurality of charge-pump stages at a location other than the common primary circuit node.

11. The method of claim 9 , wherein each of the charge-pump stages comprises a silicon-on-insulator (SOI) device.

12. The method of claim 9 , wherein selectively driving charge between stages of a plurality of series-connected charge-pump stages comprises receiving a control input from a clock driver circuit.

13. The method of claim 9 , wherein selectively removing charge comprises controlling a plurality of transistors arranged in a cascaded array in the discharge circuit, wherein each of the plurality of transistors is connected to one of the plurality of charge pump stages.

14. The method of claim 13 , wherein selectively removing charge comprises controlling a diode connected between a gate and a drain of each of the plurality of transistors.

15. The method of claim 9 , wherein selectively driving charge between stages of the plurality of series-connected charge-pump stages comprises:

measuring a present charge state at the common primary circuit node by extrapolating the present charge state from a voltage measurement taken at one of the plurality of charge-pump stages; and

driving charge between the stages of a plurality of series-connected charge-pump stages if the present charge state is less than a desired charge state.

16. A micro-electro-mechanical systems (MEMS) device comprising:

at least one fixed electrode;

a movable beam including at least one movable electrode that is spaced apart from the at least one fixed electrode and is movable with respect to the at least one fixed electrode;

a plurality of series-connected charge-pump stages connected, at a first end, to a supply voltage node and, at a second end, to a common primary circuit node, wherein the common primary circuit node is connected to one of the at least one movable electrode or the at least one fixed electrode;

a discharge circuit, comprising a plurality of sub-circuits or circuit elements, the discharge circuit being connected, at a first discharge end, to the common primary circuit node and, at a second discharge end, to a reference, wherein the discharge circuit is configured to selectively remove charge from the common primary circuit node; and

a voltage measurement device configured to measure a present charge state at the common primary circuit node;

wherein the voltage measurement device is connected in communication with one of the plurality of charge-pump stages; and

wherein the voltage measurement device is configured to extrapolate the present charge state at the common primary circuit node from a voltage measurement taken at the one of the plurality of charge-pump stages.

17. The micro-electro-mechanical systems (MEMS) device of claim 16 , wherein the discharge circuit is also connected to the plurality of charge-pump stages at a location other than the common primary circuit node.

18. The micro-electro-mechanical systems (MEMS) device of claim 16 , wherein each of the charge-pump stages comprises a silicon-on-insulator (SOI) device.

19. The micro-electro-mechanical systems (MEMS) device of claim 16 , wherein the plurality of charge-pump stages are positioned substantially beneath the movable beam.

20. The micro-electro-mechanical systems (MEMS) device of claim 16 , wherein the discharge circuit comprises a plurality of transistors arranged in a cascaded array between the common primary circuit node and a reference, wherein each of the plurality of transistors is connected to one of the plurality of charge pump stages.

21. The micro-electro-mechanical systems (MEMS) device of claim 20 , wherein the discharge circuit comprises a diode connected between a gate and a drain of each of the plurality of transistors.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 24, 2022
From: WISPRY, INC.
To: AAC TECHNOLOGIES PTE. LTD.
Reel/Frame 059096/0617 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 31, 2020
From: ZIMLICH, DAVID; CHEUNG, VINCENT
To: WISPRY, INC.
Reel/Frame 052279/0263 →
Continuity (4)
Continuation 15940458 · Mar 29, 2018
Continuation PCTUS2018000069 · Feb 16, 2018
Provisional Application 62460003 · Feb 16, 2017
Related Publication 20200228004A1 · Jul 16, 2020