Semiconductor structure and method of fabricating the same
View Patent ↗A structure adapted to optical coupled to an optical fiber includes a photoelectric integrated circuit die, an electric integrated circuit die, a waveguide die and an insulating encapsulant. The electric integrated circuit die is over and electrically connected to the photoelectric integrated circuit die. The waveguide die is over and optically coupled to the photoelectric integrated circuit die, wherein the waveguide die includes a plurality of semiconductor pillar portions extending from the optical fiber to the photoelectric integrated circuit die. The insulating encapsulant laterally encapsulates the electric integrated circuit die and the waveguide die.
1. A method, comprising:
providing an electric integrated circuit die and a waveguide die over a photoelectric integrated circuit die, wherein the waveguide die comprises a semiconductor base portion and a plurality of semiconductor pillar portions protruding from the semiconductor base portion, and the plurality of semiconductor pillar portions are between the semiconductor base portion and the photoelectric integrated circuit die;
forming an encapsulation material over the photoelectric integrated circuit die to encapsulate the electric integrated circuit die and the waveguide die; and
grinding the encapsulation material and the waveguide die to remove the semiconductor base portion until the plurality of semiconductor pillar portions are revealed, such that an insulating encapsulant laterally encapsulating the electric integrated circuit die and the waveguide die is formed,
wherein providing the waveguide die comprises:
patterning a semiconductor substrate to form the plurality of semiconductor pillar portions in the semiconductor substrate;
forming a dielectric layer over the semiconductor substrate, wherein forming the dielectric layer over the semiconductor substrate comprises:
forming a dielectric material covering the plurality of semiconductor pillar portions; and
grinding portions of the dielectric material to reveal the plurality of semiconductor pillar portions, wherein the dielectric layer and the plurality of semiconductor pillar portions are coplanar after the dielectric material is being grinded; and
singulating the semiconductor substrate and the dielectric layer.
2. The method as claimed in claim 1 , wherein a first bonding layer is formed on the photoelectric integrated circuit die, and a second bonding layer is formed on the waveguide die, and the waveguide die is bonded to the photoelectric integrated circuit die through the first bonding layer and the second bonding layer.
3. The method as claimed in claim 1 , further comprising:
recessing the insulating encapsulant, such that a top surface of the insulating encapsulant is lower than a top surface of the waveguide die.
4. A method, comprising:
providing an electric integrated circuit die and a semiconductor substrate over a photoelectric integrated circuit die;
forming an encapsulation material over the photoelectric integrated circuit die to encapsulate the electric integrated circuit die and the semiconductor substrate; and
patterning the semiconductor substrate to form a waveguide die comprising a plurality of semiconductor pillar portions after forming the encapsulation material over the photoelectric integrated circuit die.
5. The method as claimed in claim 4 further comprising:
before patterning the semiconductor substrate to form the waveguide die, grinding the encapsulation material until the electric integrated circuit die and the semiconductor substrate are revealed, such that an insulating encapsulant laterally encapsulating the electric integrated circuit die and the semiconductor substrate is formed.
6. The method as claimed in claim 2 , wherein forming the second bonding layer on the waveguide die comprises:
forming the second bonding layer on the plurality of semiconductor pillar portions and the dielectric layer.
7. The method as claimed in claim 1 , wherein providing the waveguide die over the photoelectric integrated circuit die comprises:
forming a bonding layer on the grinded dielectric material and the plurality of semiconductor pillar portions revealed by the grinded dielectric material; and
bonding the waveguide die to the photoelectric integrated circuit die through the bonding layer.
8. The method as claimed in claim 7 , wherein the bonding layer is in contact with the grinded dielectric material and the plurality of semiconductor pillar portions revealed by the grinded dielectric material.
9. The method as claimed in claim 1 , wherein the encapsulation material contacts the semiconductor base portion and the dielectric layer before grinding the encapsulation material and the waveguide die.
10. The method as claimed in claim 1 , wherein the insulating encapsulant contacts the dielectric layer after grinding the encapsulation material and the waveguide die.
11. The method as claimed in claim 1 , wherein the plurality of semiconductor pillar portions and the dielectric layer have the same height.
12. The method as claimed in claim 1 , wherein the dielectric layer contacts the plurality of semiconductor pillar portions.
13. The method as claimed in claim 4 , wherein providing the semiconductor substrate over the photoelectric integrated circuit die comprises:
forming a bonding layer on the semiconductor substrate; and
bonding the semiconductor substrate to the photoelectric integrated circuit die through the bonding layer, and
wherein the plurality of semiconductor pillar portions formed by patterning the semiconductor substrate are in contact with the bonding layer.
14. The method as claimed in claim 4 , wherein providing the semiconductor substrate over the photoelectric integrated circuit die comprises:
forming a first bonding layer on the photoelectric integrated circuit die;
forming a second bonding layer on the semiconductor substrate; and
bonding the semiconductor substrate to the photoelectric integrated circuit die through the second bonding layer and the first bonding layer.
15. The method as claimed in claim 14 , wherein a width of the second bonding layer is wider than a width of the first bonding layer.
16. The method as claimed in claim 15 , wherein the width of the second bonding layer is equal to a width of the semiconductor substrate.
17. The method as claimed in claim 4 , wherein patterning the semiconductor substrate comprises:
patterning the semiconductor substrate to form a plurality of first semiconductor pillar portions arranged in array and a second semiconductor pillar portion encircling the first semiconductor pillar portions.
18. A method, comprising:
providing an electric integrated circuit die and a waveguide die over a photoelectric integrated circuit die, wherein the waveguide die comprises a semiconductor base portion, a plurality of semiconductor pillar portions protruding from the semiconductor base portion, and a dielectric layer encapsulating the plurality of semiconductor pillar portions, wherein the plurality of semiconductor pillar portions and the dielectric layer have the same thickness;
forming an encapsulation material over the photoelectric integrated circuit die to encapsulate the electric integrated circuit die and the waveguide die, wherein the encapsulation material contacts the semiconductor base portion and the dielectric layer; and
grinding the encapsulation material and the waveguide die to remove the semiconductor base portion until the plurality of semiconductor pillar portions and the dielectric layer are revealed, such that an insulating encapsulant laterally encapsulating the electric integrated circuit die and the waveguide die is formed.
19. The method as claimed in claim 18 , wherein the dielectric layer contacts the plurality of semiconductor pillar portions.
20. The method as claimed in claim 18 , further comprising:
recessing the insulating encapsulant, such that a top surface of the insulating encapsulant is lower than a top surface of the waveguide die.