Over and under interconnects
Techniques are disclosed herein for creating over and under interconnects. Using techniques described herein, over and under interconnects are created on an IC. Instead of creating signaling interconnects and power/ground interconnects on a same side of a chip assembly, the signaling interconnects can be placed on an opposing side of the chip assembly as compared to the power interconnects.
1. A device comprising:
a chip having a first side and an opposite second side, the chip comprising power/ground interconnects on the first side and a signal interconnect on the second side, wherein:
the power/ground interconnects are capable of providing power and ground signaling for the chip; and
the signal interconnect is capable of providing chip signaling for the chip;
a heat spreader/sink component attached to the first side of the chip, wherein the power/ground interconnects are located between the chip and the heat spreader/sink component; and
a power management chip directly connected to the heat spreader/sink component, wherein:
the power management chip is capable of managing the power and ground signaling for the chip; and
an electrical path is formed for providing the power and ground signaling from the power management chip, through the heat spreader/sink component, and to the power/ground interconnects.
2. The device of claim 1 , wherein the power management chip includes a first power connector configured to connect to a power supply by connecting to a second power connector.
3. The device of claim 1 , further comprising a structural component that is coupled to the signal interconnect, wherein the structural component includes a plurality of signal passthrough that is aligned with the signal interconnect.
4. The device of claim 3 , wherein the structural component includes one or more capacitors.
5. The device of claim 1 , wherein the signal interconnect includes a capacitive coupling component that is configured to couple to an active interposer.
6. The device of claim 1 , wherein the signal interconnect includes a capacitive coupling component, configured to couple to a pin.
7. The device of claim 1 , wherein:
the signal interconnect is a first signal interconnect;
the chip comprises a second signal interconnect on the second side of the chip; and
the device comprises a cable connected to the first signal interconnect.
8. The device of claim 7 , further comprising a capacitive coupling component connected to the second signal interconnect.
9. The device of claim 1 , wherein:
the heat spreader/sink component comprises a power section, a ground section, and an insulator.
10. The device of claim 9 , wherein the power management chip is connected to a bottom side of the heat spreader/sink component and is further connected to the power section and the ground section of the heat spreader/sink component.
11. The device of claim 1 , further comprising a chip support comprising a capacitor attached to the first side of the chip, wherein the chip support is located between the power/ground interconnects and the heat spreader/sink component.
12. The device of claim 11 , further comprising joining sections and thermally conductive underfill sections between the heat spreader/sink component and the chip support, wherein:
the joining sections and thermally conductive underfill sections are coupled to the chip support;
the heat spreader/sink component comprises a power section and a ground section; and
the power management chip is directly connected to a bottom side of the heat spreader/sink component and is further connected to the power section and the ground section of the heat spreader/sink component.
13. The device of claim 11 , wherein the capacitor has an effective capacitance per unit area in a range of between 5 nF/mm 2 and 1000 nF/mm 2 .
14. The device of claim 11 , wherein the capacitor has an effective capacitance in a range between about 0.5 nF and 150 nF.
15. The device of claim 11 , wherein the capacitor has an effective capacitance per unit area in a range of between 100 nF/mm 2 to 20 μF/mm 2 .
16. The device of claim 11 , wherein the capacitor has an effective capacitance per unit area in a range of between 1 nF/mm 2 and 1 μF/mm 2 .
17. The device of claim 1 , further comprising a chip support comprising a plurality of capacitors located on the first side of the chip, wherein the chip support is between the power/ground interconnects and the heat spreader/sink component.
18. A method comprising:
attaching a chip support comprising a capacitor to a first side of a chip;
attaching a heat spreader/sink component to the chip support such that the chip support is located between the first side of the chip and the heat spreader/sink component;
directly connecting a power management chip to the heat spreader/sink component, wherein the power management chip connects to a power supply;
providing power and ground signaling to the chip through power/ground interconnects, wherein the power/ground interconnects are located on the first side of the chip;
managing the power and ground signaling for the chip using the power management chip; and
providing chip signaling to the chip through one or more signal interconnects, wherein the one or more signal interconnects are located on a second side of the chip that is opposite to the first side.
19. The method of claim 18 , further comprising coupling a structural component to the one or more signal interconnects such that a plurality of signal passthroughs of the structural component are aligned with individual ones of the one or more signal interconnects.
20. The method of claim 18 , wherein:
the one or more signal interconnects include capacitive coupling components; and
the method further comprises coupling the capacitive coupling components to a plurality of pins connected to a socket.
21. The method of claim 18 , wherein attaching the chip support comprising the capacitor to the first side of the chip comprises coupling the chip support to the power/ground interconnects.