Semiconductor storage device and method of controlling the same

1. A semiconductor storage device comprising:

a plurality of memory chips, at least one of the memory chips including a first controller configured to be shifted to a wait state of generating a peak current, before generating the peak current in accordance with a command; and

a control chip including a second controller configured to control whether or not to shift the first controller to the wait state, based on a number of memory chips operating to overlap with one another.

2. The device of claim 1 , wherein

the memory chips include electrodes provided to electrically connect the memory chips that are stacked on one another, and

the second controller searches a state of the first controller through the electrodes.

3. The device of claim 1 , wherein

the control chip includes a plurality of counters, at least one of the counters generating a count value that corresponds to a time period of generating the peak current, and

the second controller controls issuance of a cancel instruction for the wait state to the first controller that has been shifted to the wait state, based on the count value by a counter.

4. The device of claim 3 , wherein the second controller controls the issuance of the cancel instruction so as to permit overlapping of peak currents generated from the memory chips by a number of the counters.

5. The device of claim 4 , wherein,

when a number of overlapping peak currents reaches the number of the counters, the second controller issues the cancel instruction to a memory chip from which the wait state is first detected through a search subsequent to reaching the number of the counters, or issues the cancel instruction to a memory chip from which the wait state is first detected through the search executed after the counters become available again subsequent to the reaching to the number of the counters.

6. The device of claim 3 , wherein

the second controller changes a limit value for limiting a number of available counters according to a change request for changing the limit value, and

the second controller controls the issuance of the cancel instruction so as to permit overlapping of peak currents generated from the memory chips by the limit value.

7. The device of claim 3 , wherein

the second controller changes a limit value for limiting a number of available counters, when a number of memory chips that operate to overlap with one another in accordance with a predetermined command reaches an upper limit value, and

the second controller controls the issuance of the cancel instruction so as to permit overlapping of peak currents generated from the memory chips by the limit value.

8. The device of claim 7 , wherein the second controller changes the upper limit value according to a change request for changing the upper limit value.

9. The device of claim 1 , wherein the first controller receives a selection request to select a command for applying the wait state, and is shifted to the wait state before generating the peak current in accordance with the command that is selected based on the selection request.

10. The device of claim 1 , wherein the second controller controls whether or not to shift the first controller to the wait state, based on a result of comparison between a threshold and the number of memory chips operating to overlap with one another.

11. The device of claim 1 , wherein

the second controller controls whether or not to shift the first controller to the wait state, based on a result of a comparison between a threshold and the number of memory chips operating to overlap with one another, and

the second controller changes the threshold according to a change request for changing the threshold.

12. The device of claim 1 , wherein

the peak current includes a first peak current that is generated in accordance with a first command from a first channel and a second peak current that is generated in accordance with a second command from a second channel, and

the second controller searches a state of the first controller, controls issuance of a cancel instruction for the wait state to the first controller that has been shifted to the wait state regarding the first command based on a result of the search of the state of the first controller regarding the first command, and controls the issuance of the cancel instruction regarding the second command based on the result of the search regarding the second command.

13. The device of claim 1 , wherein the second controller includes a first mode in which the second controller controls a continuance time period of current consumption to a first time period, and a second mode in which the second controller controls the continuance time period of current consumption to a second time period that is different from the first time period.

14. The device of claim 1 , wherein the second controller controls issuance of a cancel instruction for the wait state to the first controller that has been shifted to the wait state regarding a predetermined command, based on a priority level given to the predetermined command.

15. The device of claim 1 , wherein the command is regarding a program operation, a read operation, or an erase operation.

16. The device of claim 1 , wherein the command is regarding an erase operation.

17. The device of claim 1 , wherein the command is regarding a program operation.

18. The device of claim 1 , wherein the second controller is starting up in response to the command.

19. The device of claim 1 , wherein the second controller starts searching a state of the first controller in response to the command.

20. The device of claim 1 , wherein, the second controller configured to search a state of the first controller and control, based on a result of searching the state of the first controller, whether or not to issue a cancel instruction for the wait state to the first controller that has been shifted to the wait state.