Memory devices configured to provide external regulated voltages

1. A memory system, comprising:

a power supply configured to provide a supply voltage to a memory device,

the memory device including:

one or more external inputs configured to receive the supply voltage;

a voltage regulator configured to receive the supply voltage from the one or more external inputs and to output an output voltage;

one or more memories configured to receive the output voltage from the voltage regulator;

one or more external outputs configured to receive the output voltage from the voltage regulator and to supply the output voltage to one or more connected devices; and

the one or more connected devices, wherein the one or more connected devices are configured to receive the output voltage from the one or more external outputs and do not receive the supply voltage from the power supply,

wherein the voltage regulator comprises a power management integrated circuit (PMIC) that includes one or more registers configured to store information corresponding to the output voltage, wherein the output voltage comprises a plurality of output voltages, and wherein the information comprises a first order in which the plurality of output voltages are powered up, first delays corresponding to the first order, a second order in which the plurality of output voltages are powered down, and second delays corresponding to the second order.

2. The memory system of claim 1 ,

wherein the output voltage comprises a first output voltage and a second output voltage,

wherein the one or more memories are configured to receive the second output voltage from the voltage regulator, and

wherein the one or more external outputs are configured to receive the first output voltage from the voltage regulator and to supply the first output voltage to the one or more connected devices.

3. The memory system of claim 2 ,

wherein the one or more external outputs are a first one or more external outputs,

wherein the one or more connected devices comprise first one or more connected devices and second one or more connected devices,

further comprising a second one or more external outputs, and

wherein the second one or more external outputs are configured to receive the second output voltage from the voltage regulator and to supply the second output voltage to the second one or more connected devices.

4. The memory system of claim 1 ,

wherein the voltage regulator comprises a first voltage regulator and a second voltage regulator,

wherein the output voltage comprises a first output voltage and a second output voltage,

wherein the one or more memories are configured to receive the first output voltage from the voltage regulator, and

wherein the one or more external outputs are configured to receive the second output voltage from the voltage regulator and to supply the second output voltage to the one or more connected devices.

5. The memory system of claim 1 , wherein the one or more connected devices are configured to receive the output voltage from the one or more external outputs exclusive of any other power supply.

6. The memory system of claim 1 , wherein the information further comprises a corresponding voltage level for each of the plurality of output voltages, and a tolerance corresponding to each of the plurality of output voltages.

7. The memory system of claim 1 , wherein the PMIC is configured to output the information in response to receiving a command from a connected host device.

8. The memory system of claim 1 , wherein the PMIC is configured to modify the information in response to receiving a command from a connected host device.

9. The memory system of claim 1 , wherein the PMIC is configured to modify the output voltage reading the stored information.

10. The memory system of claim 8 , wherein the connected host device is a processor of the memory system.

11. The memory system of claim 10 , wherein the one or more connected devices comprise the processor.

12. The memory system of claim 1 , wherein the memory device is a memory module, and wherein the one or more external inputs and the one or more external outputs are comprised by an edge connector of the memory module.

13. The memory system of claim 12 , wherein the memory module is a dual in-line memory module (DIMM).

14. The memory system of claim 2 ,

wherein the output voltage comprises a first output voltage and a second output voltage,

wherein the one or more memories comprise one or more non-volatile memories,

wherein the memory system further comprises one or more volatile memories;

wherein the one or more volatile memories are configured to receive the first output voltage from the voltage regulator, and

wherein the one or more non-volatile memories are configured to receive the second output voltage from the voltage regulator.

15. The memory system of claim 14 , wherein the memory device is a non-volatile dual in-line memory module (NVDIMM).

16. A method for operating a memory system, comprising:

providing a supply voltage from a power supply to a memory device;

generating from the supply voltage, with a voltage regulator of the memory device, an output voltage;

providing the output voltage to one or more memories of the memory device; and

providing the output voltage to one or more connected devices external to the memory device,

wherein the one or more connected devices receive the output voltage from one or more external outputs and do not receive the supply voltage from the power supply,

wherein the voltage regulator comprises a power management integrated circuit (PMIC) that includes one or more registers configured to store information corresponding to the output voltage, wherein the output voltage comprises a plurality of output voltages, and wherein the information comprises a first order in which the plurality of output voltages are powered up, first delays corresponding to the first order, a second order in which the plurality of output voltages are powered down, and second delays corresponding to the second order.

17. The method of claim 16 ,

wherein the output voltage comprises a first output voltage and a second output voltage,

wherein providing the output voltage to one or more memories of the memory device comprises providing the second output voltage to one or more memories of the memory device, and

wherein providing the output voltage to one or more connected devices external to the memory device comprises providing the first output voltage to one or more connected devices external to the memory device.

18. A memory system, comprising:

a power supply configured to provide a supply voltage to a memory device,

the memory device including:

one or more external inputs configured to receive the supply voltage;

a voltage regulator configured to receive the supply voltage from the one or more external inputs and to output an output voltage;

one or more memories configured to receive the output voltage from the voltage regulator;

one or more external outputs configured to receive the output voltage from the voltage regulator and to supply the output voltage to one or more connected devices; and

the one or more connected devices, wherein the one or more connected devices are configured to receive the output voltage from the one or more external outputs and do not receive the supply voltage from the power supply

wherein the voltage regulator is further configured to modify the output voltage in response to receiving a command from a connected host device,

wherein the voltage regulator comprises a power management integrated circuit (PMIC) that includes one or more registers configured to store information corresponding to the output voltage, wherein the output voltage comprises a plurality of output voltages, and wherein the information comprises a first order in which the plurality of output voltages are powered up, first delays corresponding to the first order, a second order in which the plurality of output voltages are powered down, and second delays corresponding to the second order.