SEMICONDUCTOR DEVICE WITH EMBEDDED MAGNETIC STORAGE STRUCTURE AND METHOD FOR FABRICATING THE SAME

1 . A semiconductor device, comprising:

a substrate;

a fin positioned on the substrate;

a gate structure positioned on the fin;

a pair of source/drain regions positioned on two sides of the fin; and

a magnetic storage structure positioned above a drain region of the pair of source/drain regions and positioned adjacent to the gate structure;

an insulating layer deposited above the gate structure and enclosing the magnetic storage structure; and

a bit line contact positioned on a source region of the pair of source/drain regions, and penetrating the insulating layer,

wherein the magnetic storage structure comprises a bottom ferromagnetic layer positioned above the drain region and having a variable magnetic polarity, a tunnel barrier layer positioned on the bottom ferromagnetic layer, and a top ferromagnetic layer positioned on the tunnel barrier layer and having a fixed magnetic polarity.

2 . The semiconductor device of claim 1 , further comprising a bottom electrode positioned below the bottom ferromagnetic layer and positioned adjacent to the gate structure, wherein a width of the bottom electrode is greater than a width of the bottom ferromagnetic layer.

3 . The semiconductor device of claim 2 , further comprising a top electrode positioned on the top ferromagnetic layer, wherein the top electrode is formed of titanium nitride, tantalum nitride, titanium, tantalum, or a combination thereof.

4 . The semiconductor device of claim 3 , further comprising a storage node contact electrically coupled to the bottom electrode and the drain region and two gate spacers positioned on two sides of the gate structure.

5 . The semiconductor device of claim 4 , wherein the gate structure comprises a gate insulating layer positioned on the fin, a gate conductive layer positioned on the gate insulating layer, and a gate filler layer positioned on the gate conductive layer.

6 . The semiconductor device of claim 5 , further comprising an anti-ferromagnetic layer positioned between the top ferromagnetic layer and the tunnel barrier layer.

7 . The semiconductor device of claim 1 , comprising:

a plurality of fins extending along a first direction;

a plurality of gate structures positioned on the plurality of fins and extending along a second direction different from the first direction; and

a plurality of storage structures separated by an insulating material along the second direction and positioned between two adjacent gate structures.

8 . The semiconductor device of claim 7 , wherein the plurality of gate structures have flat top surfaces and protrusions towards the substrate between two adjacent fins.

9 . A semiconductor device, comprising:

a substrate;

a plurality of nanowires positioned above and parallel to a top surface of the substrate, wherein the plurality of nanowires comprises channel regions and source/drain regions positioned on each of both sides of the channel regions;

a gate stack positioned surrounding the channel regions; and

a magnetic storage structure positioned above a drain region of the plurality of nanowires and positioned adjacent to the gate stack;

wherein the magnetic storage structure comprises a bottom ferromagnetic layer positioned above the drain region and having a variable magnetic polarity, a tunnel barrier layer positioned on the bottom ferromagnetic layer, and a top ferromagnetic layer positioned on the tunnel barrier layer and having a fixed magnetic polarity.

10 . The semiconductor device of claim 9 , wherein the plurality of nanowires are arranged vertically.

11 . The semiconductor device of claim 11 , further comprising a bottom electrode positioned below the bottom ferromagnetic layer and positioned adjacent to the gate stack, wherein a width of the bottom electrode is greater than a width of the bottom ferromagnetic layer, wherein a thickness of the bottom ferromagnetic layer is between about 8 angstroms and about 13 angstroms.

12 . The semiconductor device of claim 12 , further comprising two storage spacers positioned on two sides of the top ferromagnetic layer, two sides of the tunnel barrier layer, and two sides of the bottom ferromagnetic layer.

13 . The semiconductor device of claim 13 , further comprising two contacts positioned on two sides of the gate stack and surrounding the source/drain regions of the plurality of nanowires.

14 . The semiconductor device of claim 15 , further comprising two gate spacers positioned between the two contacts and the gate stack, and a thickness of the tunnel barrier layer is between about 0.5 nanometer and about 2.0 nanometers.

15 . The semiconductor device of claim 16 , further comprising a plurality of coverage layers positioned between the channel regions of the plurality of nanowires and the gate stack, wherein a band gap of the plurality of coverage layers is smaller than a band gap of the plurality of nanowires.

16 . The semiconductor device of claim 9 , comprising:

a plurality of gate stacks positioned on the plurality of nanowires, wherein the plurality of nanowires extend along a first direction and the plurality of gate stacks extend along a second direction different from the first direction; and

a plurality of storage structures separated by an insulating material along the second direction and positioned between two adjacent gate stacks.

17 . The semiconductor device of claim 16 , wherein the plurality of gate stacks have flat top surfaces and protrusions towards the substrate between two adjacent fins.

18 . A method for fabricating a semiconductor device, comprising:

providing a substrate;

forming a fin on the substrate;

forming a pair of source/drain regions on sides of the fin;

forming a gate structure on the fin;

forming a magnetic storage structure above a drain region of the pair of source/drain regions and adjacent to the gate structure;

forming an insulating layer over the gate structure and enclosing the magnetic storage structure; and

forming a bit line contact electrically coupled to a source region of the pair of source/drain regions and penetrating the insulating layer.

19 . The method for fabricating the semiconductor device of claim 18 , wherein forming a magnetic storage structure comprises:

forming a bottom ferromagnetic layer above the drain region and having a variable magnetic polarity;

forming a tunnel barrier layer on the bottom ferromagnetic layer; and

forming a top ferromagnetic layer on the tunnel barrier layer and having a fixed magnetic polarity.

20 . The method for fabricating the semiconductor device of claim 19 , wherein forming a gate structure on the fin comprising:

forming a dummy gate structure on the fin;

forming a gate spacer on sides of the dummy gate structure;

removing the dummy gate structure to form a trench;

forming insulating material in the trench; and

forming a conductive material in the trench.