Via formation with robust hardmask removal

1. A method for fabricating a semiconductor device, comprising:

forming a dielectric stack across the base structure by forming a cap layer across the base structure, a second ILD layer on the cap layer, and a sacrificial cap layer on the second ILD layer; and

forming a patterning stack across the dielectric stack by forming a hardmask layer on the sacrificial cap layer and a dielectric layer on the hardmask layer;

etching, using the patterning stack, at least one opening and hardmask layer portions, the at least one opening defining a cavity disposed within a first interlayer dielectric (ILD) layer of a base structure adjacent to a contact of the base structure resulting from overetching due to misalignment;

redefining the cavity into a plug cavity using an etch process that partially removes the hardmask layer portions; and

forming a conductive plug within the plug cavity to protect underlying material.

2. The method of claim 1 , further comprising forming the base structure on an underlying structure, wherein the contact includes a conductive core and conductive liner in contact with the underlying structure.

3. The method of claim 2 , wherein etching the at least one opening using the patterning stack further includes:

etching the patterning stack and the sacrificial cap layer to form dielectric layer portions, the hardmask layer portions, and at least one sub-opening exposing the second ILD layer;

forming a planarization layer after the at least one sub-opening is formed;

etching through the at least one sub-opening using the planarization layer to expose the sacrificial layer;

removing remaining portions of the planarization layer after exposing the sacrificial layer; and

etching through the sacrificial cap layer to form the at least one opening.

4. The method of claim 1 , wherein forming the conductive plug further includes:

conformally depositing a second conductive liner along exposed surfaces and within the plug cavity; and

removing portions of the second conductive liner to form the conductive plug in the plug cavity using isotropic etching.

5. The method of claim 1 , wherein the hardmask layer includes titanium nitride and the dielectric layer includes silicon dioxide.

6. The method of claim 1 , further comprising forming a metallization level after the conductive plug is formed, including:

removing the hardmask layer portions and the sacrificial cap layer; and

filling the opening with conductive material.

7. The method of claim 6 , wherein the conductive material includes a conductive line and a self-aligned via underneath the conductive line, and wherein the conductive plug provides increased connectivity between the self-aligned via and the contact.

8. A method for fabricating a semiconductor device, comprising:

etching, using a patterning stack including a hardmask layer, a first opening and a second opening and hardmask layer portions, the first opening defining a cavity disposed within a first interlayer dielectric (ILD) layer of a base structure adjacent to a contact of the base structure resulting from overetching due to misalignment;

redefining the cavity into a plug cavity using an etch process that partially removes the hardmask layer portions;

conformally depositing a second conductive liner along exposed surfaces and within the plug cavity;

removing portions of the second conductive liner to form a conductive plug in the plug cavity to protect underlying material; and

forming a metallization level after the conductive plug is formed by removing the hardmask layer portions, and filling the first and second openings with conductive material.

9. The method of claim 8 , further comprising forming the base structure on an underlying structure, wherein the contact includes a conductive core and conductive liner in contact with the underlying structure.

10. The method of claim 8 , further comprising:

forming a dielectric stack across the base structure by forming a cap layer across the base structure, a second ILD layer on the cap layer, and a sacrificial cap layer on the second ILD layer; and

forming the patterning stack across the dielectric stack by forming the hardmask layer on the sacrificial cap layer and a dielectric layer on the hardmask layer;

wherein the conductive material filling the second opening is within the second ILD layer.

11. The method of claim 10 , wherein etching the first and second openings using the patterning stack further includes:

etching the patterning stack and the sacrificial cap layer to form dielectric portions, the hardmask layer portions, and a first sub-opening and a second sub-opening each exposing the second ILD layer;

forming a planarization layer after the first and second sub-openings are formed;

etching through the first sub-opening using the planarization layer while the second sub-opening is filled with the planarization layer to expose the sacrificial layer;

removing remaining portions of the planarization layer after exposing the sacrificial layer; and

etching through the sacrificial cap layer to form the first and second openings.

12. The method of claim 8 , wherein removing the portions of the second conductive liner to form the conductive plug further includes using isotropic etching.

13. The method of claim 8 , wherein the hardmask layer includes titanium nitride and the dielectric layer includes silicon dioxide.

14. The method of claim 8 , wherein the conductive material in the first opening includes a conductive line and a self-aligned via disposed on the conductive core and the conductive plug underneath the conductive line, and wherein the conductive plug provides increased connectivity between the self-aligned via and the contact.

15. The method of claim 8 , wherein the conductive material in the second opening includes a conductive line.