Power circuit that interrupts supply of power to a volatile memory in response to a signal indicating a malfunction of a processor
The present description relates to a method and a circuit for powering a volatile memory in which power pulses are sent to the memory, the duration between two pulses being shorter than a remanence time of said volatile memory.
1. A method, comprising:
storing data in a dynamic random access memory, a remanence time of the dynamic random access memory being a time during which the data are kept in the dynamic random access memory after a supply of power to the dynamic random access memory is stopped;
outputting, with a processor, a state signal including a plurality of first power pulses, wherein a first separation time between the first power pulses indicates whether or not the processor is in a malfunction state;
sending, with a power circuit, a plurality of second power pulses to the dynamic random access memory, consecutive pulses of the plurality of second power pulses being separated by a second separation time that is shorter than the remanence time of the dynamic random access memory;
receiving the state signal with the power circuit; and
interrupting the supply of the second power pulses to the dynamic random access memory in response to the first separation time of the first power pulses of the state signal from the processor being larger than the second separation time, wherein the second separation time is between 55 and 75% of the remanence time.
2. The method of claim 1 , wherein the second power pulses are periodic.
3. The method of claim 1 , wherein the second separation time is approximately 100 nanoseconds.
4. A method comprising:
sending, from a processor to a power circuit, a state signal including a plurality of first power pulses, wherein a first separation time between the first power pulses indicates whether or not the processor is in a malfunction state;
powering a dynamic random access memory that stores data by sending a plurality of second power pulses from the power circuit to the dynamic random access memory, a remanence time of the dynamic random access memory being a time during which the data are kept in the dynamic random access memory after a supply of power to the dynamic random access memory is stopped, and consecutive power pulses of the plurality of second power pulses being separated by a second separation time that is shorter than the remanence time of said dynamic random access memory; and
interrupting the supply of the second power pulses to the dynamic random access memory in response to the first separation time being larger than the second separation time, wherein the second separation time is between 55 and 75% of the remanence time.
5. The method according to claim 4 , wherein a memory of the processor stores the remanence time of the dynamic random access memory, and the processor controls the second separation times of the second power pulses based on the stored remanence time.
6. The method according to claim 4 , wherein the second pulses are periodic.
7. The method according to claim 4 , wherein the second pulses have a duration of approximately 100 nanoseconds.
8. A method, comprising:
storing data in a dynamic random access memory;
outputting, with a processor, a state signal including a plurality of first power pulses, wherein a first separation time between the first power pulses indicates whether or not the processor is in a malfunction state;
storing in a memory of the processor, a remanence time of the dynamic random access memory; and
sending, with a power circuit, a plurality of second power pulses to the dynamic random access memory, consecutive pulses of the plurality of second power pulses being separated by a second separation time that is shorter than the remanence time of the dynamic random access memory; and
interrupting the supply of the second power pulses to the dynamic random access memory in response to the first separation time being larger than the second separation time, wherein the second separation time is between 55 and 75% of the remanence time.
9. The method of claim 8 , wherein the processor controls the duration between the consecutive second power pulses based on the stored remanence time.
10. The method of claim 8 , wherein the second pulses are periodic.
11. The method of claim 8 , wherein the second separation time is approximately 100 nanoseconds.