Logical operations using memory cells
The present disclosure includes apparatuses and methods related to logical operations using memory cells. An example apparatus comprises a first memory cell controlled to invert a data value stored therein and a second memory cell controlled to invert a data value stored therein. The apparatus may further include a controller coupled to the first memory cell and the second memory cell. The controller may be configured to cause performance of a logical operation between the data value stored in the first memory cell and the data value stored in the second memory cell.
1. A method, comprising:
performing a K-input logical operation by:
charging, to a first voltage, a read digit line coupled to K three transistor (3t) memory cells associated with a memory device, wherein each one of the K 3T memory cells stores a data value corresponding to a respective one of the K-inputs;
activating read word lines corresponding to the K memory cells;
while at least one of the read word lines corresponding to the K memory cells is activated, enabling a sense amplifier coupled to the read digit line, wherein subsequent to enabling the sense amplifier, a result of the K-input logical operation resides in the sense amplifier, and wherein a controller is configured to cause the sense amplifier to:
sense a particular logic value responsive to one or more of the K memory cells storing a first data value;
sense a different logic value responsive to all of the K memory cells storing a second data value that is different than the first data value; and
write a result of the K-input logical operation or a complement of the result of the K-input logical operation to a number of memory cells coupled to a write digit line of the memory device based on enabling a first transistor coupled to the sense amplifier or enabling a second transistor coupled to the sense amplifier.
2. The method of claim 1 , wherein the method includes activating the read word lines corresponding to the memory cells simultaneously.
3. The method of claim 1 , wherein the K memory cells are nondestructive read memory cells such that the activating the read word lines and enabling the sense amplifier does not destroy the data values stored in the K memory cells.
4. The method of claim 1 , wherein the K-input logical operation is a K-input logical NOR operation.
5. An apparatus, comprising:
an array of three transistor (3T) memory cells; and
a controller coupled to the array of 3T memory cells, the controller configured to cause:
performance of a K-input logical operation by:
charging, to a first voltage, a read digit line coupled to K memory cells, wherein each one of the K memory cells stores a data value corresponding to a respective one of the K-inputs;
activating read word lines corresponding to the K memory cells;
while at least one of the read word lines corresponding to the K memory cells is activated, enabling a sense amplifier coupled to the read digit line, wherein subsequent to enabling the sense amplifier, a result of the K-input logical operation resides in the sense amplifier, and wherein the controller is configured to cause the sense amplifier to:
sense a particular logic value responsive to one or more of the K memory cells storing a first data value;
sense a different logic value responsive to all of the K memory cells storing a second data value that is different than the first data value; and
enable a first transistor coupled to the sense amplifier to write a result of the K-input logical operation to memory cells coupled to respective memory cells of a first write row line and enable a second transistor coupled to the sense amplifier to write a complement of the result of the K-input logical operation to respective memory cells of a second write row line.
6. The apparatus of claim 5 , wherein the controller is configured to cause the read word lines corresponding to the memory cells to be activated simultaneously.
7. The apparatus of claim 5 , wherein the K memory cells are three transistor (3T) dynamic random-access memory (3T DRAM) cells.
8. The apparatus of claim 5 , wherein the K memory cells are nondestructive read memory cells such that the activating the read word lines and enabling the sense amplifier does not destroy the data values stored in the K memory cells.
9. The apparatus of claim 5 , wherein the K-input logical operation is a K-input logical NOR operation.
10. The apparatus of claim 5 , wherein the controller is configured to cause the result of the K-input logical operation to be shifted from the sense amplifier to a different sense amplifier associated with the memory cells.
11. The apparatus of claim 5 , wherein the controller is configured to cause the complement of a result of the K-input logical operation to be transferred to a different one of the K memory cells.
12. The apparatus of claim 5 , wherein the sense amplifier is a sense amplifier among a plurality of sense amplifiers coupled to respective memory cells among the K memory cells.
13. A system, comprising:
a memory device comprising:
an array of three transistor (3T) memory cells; and
a controller coupled to the array of 3T memory cells, wherein the controller is configured to cause performance of a K-input logical operation by:
charging, to a first voltage, a read digit line coupled to K memory cells, wherein each one of the K memory cells stores a data value corresponding to a respective one of the K-inputs;
activating read word lines corresponding to the K memory cells;
while at least one of the read word lines corresponding to the K memory cells is activated, enabling a sense amplifier coupled to the read digit line, wherein subsequent to enabling the sense amplifier, a result of the K-input logical operation resides in the sense amplifier, and wherein the controller is configured to cause the sense amplifier to:
sense a particular logic value responsive to one or more of the K memory cells storing a first data value;
sense a different logic value responsive to all of the K memory cells storing a second data value that is different than the first data value; and
enable a first transistor coupled to the sense amplifier to write a result of the K-input logical operation to memory cells coupled to respective memory cells of a first write row line and enable a second transistor coupled to the sense amplifier to write a complement of the result of the K-input logical operation to respective memory cells of a second write row line.
14. The system of claim 13 , wherein the controller is configured to cause the read word lines corresponding to the memory cells to be activated simultaneously.
15. The system of claim 13 , wherein the controller is configured to cause the read word lines corresponding to the memory cells to be activated at different times.
16. The system of claim 13 , wherein the K-input logical operation is a K-input logical NOR operation.
17. The system of claim 13 , wherein the controller is configured to cause the complement of a result of the K-input logical operation to be transferred to a different one of the K memory cells.
18. The system of claim 13 , wherein the controller is configured to cause the result of the K-input logical operation to be shifted from the sense amplifier to a different sense amplifier associated with the memory cells.
19. The system of claim 13 , wherein the K memory cells are nondestructive read memory cells such that the activating the read word lines and enabling the sense amplifier does not destroy the data values stored in the K memory cells.