Reactive droop limiter
During normal operation of a processor, voltage droop is likely to occur and there is, therefore, a need for techniques for rapidly addressing this droop so as to reduce the probability of circuit timing failures. This problem is addressed by provided an apparatus that is configured to detect the droop and react to mitigate the droop. The apparatus includes a frequency divider that is configured to receive an output of a clock signal generator (e.g. a phase locked loop) and produce an output signal in which a predefined fraction of the clock pulses in the output of the clock signal generator are removed from the output signal. By reducing the frequency of the clock signal in this way (as may be understood by examining equation 3) V DD is increased, hence mitigating the voltage droop. This technique provides a fast throttling mechanism that prevents excessive V DD droop across the processor.
1. A method of controlling the frequency of a clock signal for a processor, the method comprising:
receiving from a clock generator, a first processor clock signal for supplying to a processor, the first processor clock signal being of a first frequency;
receiving an indication of voltage droop in a voltage supplied to the processor;
in response to the indication of the voltage droop, blocking the first processor clock signal from being supplied to the processor for a predefined number of clock pulses of the first processor clock signal;
subsequently, in response to the indication of the voltage droop, removing a proportion of clock pulses from the first processor clock signal to generate a second processor clock signal of a second frequency, wherein the second frequency is lower than the first frequency; and
providing the second processor clock signal to the processor.
2. The method as claimed in claim 1 , wherein the step of, in response to the indication of the voltage droop, removing a proportion of clock pulses comprises:
determining from the indication of the voltage droop that the voltage droop exceeds a predefined threshold; and
in response to the voltage droop exceeding the predefined threshold, performing the removing the proportion of clock pulses.
3. The method as claimed in claim 1 , wherein the method comprises, following the step of removing the proportion of clock pulses from the first processor clock signal, adjusting the second processor clock signal to increase the second frequency, the adjusting the second processor clock signal comprising decreasing the proportion of clock pulses removed from the first processor clock signal.
4. The method as claimed in claim 1 , wherein the second frequency F out is related to the first frequency F in by:
F
o
u
t
=
N
2
5
6
F
i
n
wherein N is an integer.
5. The method as claimed in claim 1 , wherein the proportion of clock pulses is dependent upon a magnitude of the voltage droop contained in the indication of voltage droop in the voltage supplied to the processor.
6. The method as claimed in claim 1 , wherein the method comprises measuring a supply voltage to produce the indication of the voltage droop.
7. The method as claimed in claim 6 , wherein the step of measuring the supply voltage comprises using an analog to digital convertor to measure the supply voltage.
8. The method as claimed in claim 1 , wherein the step of detecting voltage droop in the supply voltage comprises using a tap sampled delay line to measure a change in a clock edge position of the first clock signal in the tap sampled delay line, wherein the tap sampled delay line is powered by a same power supply that supplies the voltage to the processor.
9. The method as claimed in claim 8 , wherein the step of detecting voltage droop in the supply voltage comprises:
using a further delay line to delay the first clock signal to produce a delayed clock signal, wherein the further delay line is powered by a same power supply that supplies the voltage to the processor; and
using the delayed clock signal to determine when to sample the first clock signal in the tap sample delay line to make a measurement of the clock edge position.
10. The method as claimed in claim 1 , comprising receiving the second clock signal at the processor;
propagating the second clock signal along copper wires of the processor for clocking one or more components of the processor.
11. The method as claimed in claim 10 , wherein the copper wires have a thickness of greater than 0.2 micrometres.
12. The method as claimed in claim 10 , wherein the one or more components of the processor comprise a plurality of processing units.
13. A computer system comprising droop mitigation circuitry:
comprising controller circuitry and clock signal modification circuitry, the clock signal modification circuitry configured to receive from a clock generator, a first processor clock signal for supplying to a processor, the first processor clock signal being of a first frequency;
wherein the controller circuitry is configured to receive an indication of voltage droop in a voltage supplied to the processor,
wherein the clock signal modification circuitry is configured to:
in response to the indication of the voltage droop, block the first processor clock signal from being supplied to the processor for a predefined number of clock pulses of the first processor clock signal;
subsequently, in response to the indication of the voltage droop received at the controller circuitry, remove a proportion of clock pulses from the first processor clock signal to generate a second processor clock signal of a second frequency, wherein the second frequency is lower than the first frequency; and
provide the second processor clock signal to the processor.
14. The computer system as claimed in claim 13 , wherein the controller circuitry is configured to:
determine from the indication of the voltage droop that the voltage droop exceeds a predefined threshold; and
in response to the determination that the threshold is exceeded, provide an indication that the threshold is exceeded to the clock signal modification circuitry,
wherein the step of, in response to the indication of the voltage droop received at the controller circuitry, remove the proportion of clock pulses comprises the clock signal modification circuitry removing the proportion of clock pulses in response to the received indication that the threshold is exceeded.
15. The computer system as claimed in claim 13 , wherein the controller circuitry is configured to: in response to the determination that the threshold is exceeded, provide an indication that the threshold is exceeded to the clock signal modification circuitry, wherein the indication that the threshold is exceeded comprises an indication of the proportion of clock pulses.
16. The computer system as claimed in claim 13 , wherein the computer system comprises a droop detector configured to measure a supply voltage to produce the indication of the voltage droop.
17. The computer system as claimed in claim 16 , wherein the droop detector comprises one or more analog to digital convertors configured to measure the supply voltage droop.
18. The computer system as claimed in claim 16 , wherein the droop detector comprises a tap sampled delay line configured to measure the voltage droop by measuring a change in a clock edge position of the first clock signal in the tap sampled delay line, wherein the tap sampled delay line is powered by a same power supply that supplies the voltage to the processor.
19. The computer system as claimed in claim 13 , comprising the processor configured to:
receive the second clock signal; and
propagate the second clock signal along copper wires of the processor for clocking one or more components of the processor.
20. The computer system as claimed in claim 19 , wherein the droop mitigation circuitry is located at an entry point of the second clock signal to the processor.