IP Library Granted Patent US 10,992,288
Granted Patent B2
US 10,992,288 · App. 16/843,624 · Granted Apr 27, 2021

Oscillator device

Inventor: Lei Zou (Viken, NO)
Assignee: TDK Corporation
H03K3/0315H03K3/011H03K3/0231H03K3/354H03K5/134H03K2005/00208H03K2005/00221
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Quick Facts
Patent No.
US 10,992,288
App. No.
16/843,624
Granted
Apr 27, 2021
Kind
B2
Abstract

In an embodiment an oscillator device includes a ring oscillator circuit with at least one delay stage with an output of a last delay stage fed back to an input of a first delay stage, wherein each of the delay stages is configured to receive a charging current and to provide a delay that is dependent on the charging current and at least one of the delay stages includes a metal-oxide-semiconductor field-effect transistor and a bias circuit including an output terminal coupled to an input terminal of the ring oscillator circuit, wherein the bias circuit is configured to receive a temperature-independent reference voltage and includes a current source with a main NMOS-transistor, the current source configured to provide a control current to the ring oscillator circuit which is proportional to a difference of the temperature-independent reference voltage and a gate-source voltage of the main NMOS-transistor, and wherein the gate-source voltage of the main NMOS-transistor includes a negative temperature coefficient.

Claims (39)

1. An oscillator device comprising:

a ring oscillator circuit with at least one delay stage with an output of a last delay stage fed back to an input of a first delay stage, wherein each of the delay stages is configured to receive a charging current and to provide a delay that is dependent on the charging current and at least one of the delay stages comprises a metal-oxide-semiconductor field-effect transistor; and

a bias circuit comprising an output terminal coupled to an input terminal of the ring oscillator circuit,

wherein the bias circuit is configured to receive a temperature-independent reference voltage and comprises a current source with a main NMOS-transistor, the current source configured to provide a control current to the ring oscillator circuit which is proportional to a difference of the temperature-independent reference voltage and a gate-source voltage of the main NMOS-transistor,

wherein the gate-source voltage of the main NMOS-transistor comprises a negative temperature coefficient, and

wherein a transistor aspect ratio width/length of the main NMOS-transistor is adjusted such that the control current of the bias circuit comprises a desired positive temperature coefficient for compensating temperature-dependent delay drifts of the delay stages.

2. The oscillator device according to claim 1 , wherein each of the delay stages comprises a current-starved delay element.

3. The oscillator device according to claim 2 , wherein each delay stage comprises a current starving circuit coupled to the delay element, and wherein the current starving circuit comprises a first transistor and a second transistor and the first and second transistors are arranged and configured to control the charging current provided to the delay element.

4. The oscillator device according to claim 2 , wherein the delay element comprises an inverter circuit or is an inverter circuit.

5. The oscillator device according to claim 4 , wherein the inverter circuit comprises an n-type metal oxide semiconductor transistor and a p-type metal oxide semiconductor transistor coupled as the inverter circuit.

6. The oscillator device according to claim 1 , wherein the bias circuit further comprises:

a differential amplifier configured to compare the temperature-independent reference voltage with a measurement voltage;

a feedback transistor with a gate-drain path of the feedback transistor being arranged in a negative feedback loop of the differential amplifier; and

a resistor network, wherein a drain of the feedback transistor is coupled to a first terminal of the resistor network and a drain of the main NMOS-transistor is coupled to a second terminal of the resistor network and the measurement voltage is tapped at the first terminal of the resistor network.

7. The oscillator device according to claim 6 , wherein the resistor network consists of a single resistor.

8. The oscillator device according to claim 6 , wherein the resistor network comprises multiple resistors and switches for adjusting a resistor value of the resistor network effective between the first terminal and the second terminal of the resistor network.

9. The oscillator device according to claim 6 , wherein a respective resistor is an un-silicided P polysilicon resistor.

10. The oscillator device according to claim 1 , wherein the bias circuit comprises at least one transistor branch arranged parallel to the main NMOS-transistor, and wherein the at least one transistor branch comprises a further NMOS-transistor and a switch.

11. The oscillator device according to claim 1 , wherein the bias circuit is configured to operate the main NMOS-transistor in a strong inversion region.

12. The oscillator device according to claim 1 , wherein the reference voltage is larger than the gate-source voltage.

13. An oscillator device comprising:

a ring oscillator circuit with at least one delay stage with an output of a last delay stage fed back to an input of a first delay stage, wherein each of the delay stages is configured to receive a charging current and to provide a delay that is dependent on the charging current and at least one of the delay stages comprises a metal-oxide-semiconductor field-effect transistor; and

a bias circuit comprising an output terminal coupled to an input terminal of the ring oscillator circuit,

wherein the bias circuit is configured to receive a temperature-independent reference voltage and comprises a current source with a main NMOS-transistor, the current source being configured to provide a control current to the ring oscillator circuit which is proportional to a difference of the temperature-independent reference voltage and a gate-source voltage of the main NMOS-transistor,

wherein the gate-source voltage of the main NMOS-transistor comprises a negative temperature coefficient,

wherein the bias circuit further comprises a differential amplifier configured to compare the temperature-independent reference voltage with a measurement voltage, a feedback transistor with a gate-drain path of the feedback transistor being arranged in a negative feedback loop of the differential amplifier, and a resistor network, and

wherein a drain of the feedback transistor is coupled to a first terminal of the resistor network and a drain of the main NMOS-transistor is coupled to a second terminal of the resistor network and the measurement voltage is tapped at the first terminal of the resistor network.

14. The oscillator device according to claim 13 , wherein the bias circuit is configured to operate the main NMOS-transistor in a strong inversion region.

15. The oscillator device according to claim 13 , wherein each of the delay stages comprises a current-starved delay element.

16. The oscillator device according to claim 13 , wherein a respective resistor is an un-silicided P polysilicon resistor.

17. The oscillator device according to claim 13 , wherein each of the delay stages comprises a current-starved delay element, wherein each delay stage comprises a current starving circuit coupled to the delay element, and wherein the current starving circuit comprises a first transistor and a second transistor and the first and second transistors are configured to control the charging current provided to the delay element.

18. The oscillator device according to claim 13 , wherein the resistor network consists of a single resistor.

19. The oscillator device according to claim 13 , wherein the resistor network comprises multiple resistors and switches for adjusting a resistor value of the resistor network effective between the first terminal and the second terminal of the resistor network.

20. An oscillator device comprising:

a ring oscillator circuit with at least one delay stage with an output of a last delay stage fed back to an input of a first delay stage, wherein each of the delay stages is configured to receive a charging current and to provide a delay that is dependent on the charging current and at least one of the delay stages comprises a metal-oxide-semiconductor field-effect transistor; and

a bias circuit comprising an output terminal coupled to an input terminal of the ring oscillator circuit,

wherein the bias circuit is configured to receive a temperature-independent reference voltage and comprises a current source with a main NMOS-transistor, the current source configured to provide a control current to the ring oscillator circuit which is proportional to a difference of the temperature-independent reference voltage and a gate-source voltage of the main NMOS-transistor,

wherein the gate-source voltage of the main NMOS-transistor comprises a negative temperature coefficient, and

wherein the reference voltage is larger than the gate-source voltage.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 13, 2025
From: TDK CORPORATION
To: INVENSENSE, INC.
Reel/Frame 073080/0824 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 30, 2020
From: TDK ELECTRONICS AG
To: TDK CORPORATION
Reel/Frame 054494/0914 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 22, 2020
From: ZOU, LEI
To: TDK ELECTRONICS AG
Reel/Frame 053284/0973 →