Memory system and operation method thereof

1. A memory system comprising:

an error correction code (KC) generation circuit suitable for generating an M-bit error correction code using N-bit data, where N and M are positive integers;

a memory core suitable for storing the N-bit data and the M-bit error correction code; and

an ECC circuit suitable for correcting an error of the N-bit data read from the memory core, using the M-bit error correction code read from the memory core,

wherein the ECC generation circuit generates the M-bit error correction code using an M×(N+M) check matrix,

wherein one column vector among M column vectors corresponding to the M-bit error correction code in the M×(N+M) check matrix has an odd weight, and the other M column vectors have even weights.

2. The memory system of claim 1 , wherein at most one column vector among N column vectors corresponding to the N-bit data in the M×(N+M) check matrix has an even weight, and the other N column vectors have odd weights.

3. The memory system of claim 2 , wherein the ECC circuit corrects one bit error which occurs in the N-bit data and the M-bit error correction code, which are read from the memory core, using the M-bit error correction code.

4. The memory system of claim 2 ,

wherein the ECC generation circuit, the memory core and the ECC circuit are included in a memory,

wherein the memory system further comprises a memory controller suitable for controlling the memory.

5. The memory system of claim 4 ,

wherein during a write operation, the memory controller transfers the N-bit data to the memory, and

wherein the ECC generation circuit of the memory generates the M-bit error correction code using the N-bit data, and the N-bit data and the M-bit error correction code are stored in the memory core.

6. The memory system of claim 5 ,

wherein during a read operation, the N-bit data and the M-bit error correction code, stored in the memory core, are transferred to the ECC circuit,

wherein the ECC circuit corrects an error of the N-bit data read from the memory core, using the M-bit error correction code read from the memory core, and

wherein the N-bit data whose error is corrected by the ECC circuit is transferred to the memory controller from the memory.

7. An operation method of a memory, comprising:

generating an M-bit error correction code using N-bit write data, where N and M are positive integers;

writing the N-bit write data and the M-bit error correction code to a memory core;

reading N-bit read data and an M-bit error correction code corresponding to the N-bit read data from the memory core; and

performing an error correction operation on the N-bit read data using the M-bit error correction code read from the memory core,

wherein the generating of the M-bit error correction code comprises generating the M-bit error correction code using an M×(N+M) check matrix,

wherein one column vector among M column vectors corresponding to the M-bit error correction code in the M×(N+M) check matrix has an odd weight, and the other M column vectors have even weights.

8. The operation method of claim 7 , wherein at most one column vector among the N column vectors corresponding to the N-bit data in the M×(N+M) check matrix has an even weight, and the other N column vectors have odd weights.

9. The operation method of claim 8 , further comprising transmitting the N-bit read data, on which the error correction operation has been performed, to a memory controller.

10. A memory system comprising:

an error correction code (ECC) generation circuit suitable for generating an 8-bit error correction code using N-bit data, where N is a positive integer;

a memory core suitable for storing the N-bit data and the 8-bit error correction code; and

an ECC circuit suitable for correcting an error of the N-bit data read from the memory core, using the 8-bit error correction code read from the memory core,

wherein the ECC generation circuit generates the 8-bit error correction code using an 8×(N+8) check matrix,

wherein all columns in one row of first to eighth rows of an 8×8 matrix corresponding to the 8-bit error correction code in the 8×(N+8) check matrix have a value of ‘1’, and all columns in each of the other seven rows have the same values as those in the corresponding row of the 8×8 identity matrix.

11. The memory system of claim 10 , wherein at most one column vector among the N column vectors corresponding to the N-bit data in the 8×(N+8) check matrix has an even weight, and the other N column vectors have odd weights.

12. The memory system of claim 11 , wherein the ECC circuit corrects one bit error which occurs in the N-bit data and the 8-bit error correction code, which are read from the memory core, using the 8-bit error correction code.

13. The memory system of claim 11 ,

wherein the ECC generation circuit, the memory core and the ECC circuit are included in a memory,

wherein the memory system further comprises a memory controller suitable for controlling the memory.

14. The memory system of claim 13 ,

wherein during a write operation, the memory controller transfers the N-bit data to the memory, and

wherein the ECC generation circuit of the memory generates the 8-bit error correction code using the N-bit data, and the N-bit data and the 8-bit error correction code are stored in the memory core.

15. The memory system of claim 14 ,

wherein during a read operation, the N-bit data and the 8-bit error correction code, stored in the memory core, are transferred to the ECC circuit,

wherein the ECC circuit corrects an error of the N-bit data read from the memory core, using the 8-bit error correction code read from the memory core, and

wherein the N-bit data whose error is corrected by the ECC circuit is transferred to the memory controller from the memory.

16. An operating method of error correction circuitry, the operating method comprising:

generating, through an M×(N+M) check matrix, an M-bit error correction code from N-bit data; and

avoiding mis-correcting the N-bit data, in which an error of 1-bit or greater occurs after the generating, while error-correcting the N-bit data based on the M-bit error correction code,

wherein one of M column vectors corresponding to the M-bit error correction code within the M×(N+M) check matrix is odd-weighted and all of the other M column vectors are even-weighted, and

wherein at most one of N column vectors corresponding to the N-bit data within the M×(N+M) check matrix is even-weighted and all of the other N column vectors are odd-weighted.