Test key structure
The present invention provides a test key structure, the test key structure a substrate, a plurality of test key cells disposed on the substrate, wherein each test key cell includes a first gate structure arranged along a first direction (X-axis), a first diffusion region, a second diffusion region, a connection diffusion region and a share contact arranged along a second direction (Y-axis), wherein the first gate structure crosses over the first diffusion region to form a pull-up transistor (PU), the second gate structure crosses over the second diffusion region to form a pull-down transistor (PD), and wherein the plurality of share contacts and the plurality of connection diffusion regions of the plurality of test key cells are electrically connected to each other.
1. A test key structure, comprising:
a substrate;
a plurality of test key cells disposed on the substrate, wherein each test key cell includes a first gate structure arranged along a first direction (X-axis), a first diffusion region, a second diffusion region, a connection diffusion region and a share contact arranged along a second direction (Y-axis), wherein the first gate structure crosses over the first diffusion region to form a pull-up transistor (PU), the first gate structure crosses over the second diffusion region to form a pull-down transistor (PD), and wherein the plurality of share contacts and the plurality of connection diffusion regions of the plurality of test key cells are electrically connected to each other.
2. The test key of claim 1 , wherein the first direction and the second direction are perpendicular to each other.
3. The test key of claim 1 , wherein the connection diffusion region of each test key cell and the share contact are aligned with each other along the second direction.
4. The test key of claim 1 , wherein each test key cell further comprising a second gate structure, wherein the second gate structure crosses over the second diffusion region to form a first access transistor (PG 1 ).
5. The test key of claim 4 , wherein each test key cell further comprising a third gate structure, wherein the third gate structure crosses over a third diffusion region to form a second access transistor (PG 2 ).
6. The test key of claim 4 , wherein the PG 1 and the PD are aligned with each other along the second direction.
7. The test key of claim 5 , wherein each test key cell comprises four transistors.
8. The test key of claim 5 , wherein the PU, the PD and the PG 2 are aligned with each other along the first direction.
9. The test key of claim 1 , wherein each share contact comprises vertical conductive plugs and a horizontal conductive layer.
10. The test key of claim 9 , wherein each vertical conductive plug contacts the first gate structure and the connection diffusion region simultaneously.
11. The test key of claim 1 , further comprising a plurality of SRAM cells disposed on the substrate, wherein each SRAM cell comprises at least 6 transistors, 8 transistors or 10 transistors.
12. The test key of claim 1 , wherein adjacent test key cells of the plurality of test key cells are symmetrical to each other.