Metal oxide and field-effect transistor
View Patent ↗To provide a novel material. In a field-effect transistor including a metal oxide, a channel formation region of the transistor includes a material having at least two different energy band widths. The material includes nano-size particles each with a size of greater than or equal to 0.5 nm and less than or equal to 10 nm. The nano-size particles are dispersed or distributed in a mosaic pattern.
1. A semiconductor device comprising:
a transistor comprising a channel formation region; and
a light-emitting element electrically connected to the transistor,
wherein the channel formation region comprises a first nano-size region comprising indium, gallium, and zinc and a second nano-size region comprising indium, gallium, and zinc,
wherein the number of gallium atoms in the first nano-size region is larger than the number of gallium atoms in the second nano-size region, and
wherein the first nano-size region and the second nano-size region have different crystal structures.
2. The semiconductor device according to claim 1 ,
wherein a boundary between the first nano-size region and the second nano-size region is not clear, and
wherein the first nano-size region and the second nano-size region are mixed to form a mosaic pattern.
3. The semiconductor device according to claim 1 ,
wherein an energy band width of the first nano-size region is larger than an energy band width of the second nano-size region.
4. The semiconductor device according to claim 1 ,
wherein a plurality of first nano-size regions comprising the first nano-size region and a plurality of second nano-size regions comprising the second nano-size region are included in the channel formation region.
5. A semiconductor device comprising:
a transistor comprising a channel formation region; and
a light-emitting element electrically connected to the transistor,
wherein the channel formation region comprises a first region comprising indium, gallium, and zinc and a second region comprising indium, gallium, and zinc,
wherein the number of gallium atoms in the first region is larger than the number of gallium atoms in the second region, and
wherein each of a size of the first region and a size of the second region in energy dispersive X-ray spectroscopy (EDX) mapping image is greater than or equal to 0.5 nm and less than or equal to 3 nm.
6. The semiconductor device according to claim 5 ,
wherein a boundary between the first region and the second region is not clear, and
wherein the first region and the second region are mixed to form a mosaic pattern.
7. The semiconductor device according to claim 5 ,
wherein an energy band width of the first region is larger than an energy band width of the second region.
8. The semiconductor device according to claim 5 ,
wherein a plurality of first regions comprising the first region and a plurality of second regions comprising the second region are included in the channel formation region.
9. The semiconductor device according to claim 5 ,
wherein the first region and the second region have different crystal structures.
10. A semiconductor device comprising:
a transistor comprising a channel formation region; and
a light-emitting element electrically connected to the transistor,
wherein the channel formation region comprises a first nano-size region comprising indium and tin and a second nano-size region comprising indium and tin,
wherein the number of tin atoms in the first nano-size region is larger than the number of tin atoms in the second nano-size region, and
wherein the first nano-size region and the second nano-size region have different crystal structures.
11. The semiconductor device according to claim 10 ,
wherein a boundary between the first nano-size region and the second nano-size region is not clear, and
wherein the first nano-size region and the second nano-size region are mixed to form a mosaic pattern.
12. The semiconductor device according to claim 10 ,
wherein an energy band width of the first nano-size region is larger than an energy band width of the second nano-size region.
13. The semiconductor device according to claim 10 ,
wherein a plurality of first nano-size regions comprising the first nano-size region and a plurality of second nano-size regions comprising the second nano-size region are included in the channel formation region.