Optimization processing unit having subunits that are programmably and partially connected

1. A system, comprising:

an optimization processing unit (OPU) including

a plurality of stochastic computing units, each of the plurality of stochastic computing units including a plurality of nodes and at least one multiplication unit configured to interconnect at least a portion of the plurality of nodes, each of the plurality of nodes including an oscillator selected from an analog oscillator and a digital representation of the analog oscillator, the multiplication unit multiplying an output from a node of the at least the portion of the plurality of nodes by a weight to provide a weighted output and providing the weighted output to an input of at least one other node of the at least the portion of the plurality of nodes; and

at least one programmable interconnect configured to provide weights for and to selectably couple a portion of the plurality of stochastic computing units, the at least one programmable interconnect weighting at least one response from a first stochastic computing unit of the portion of the plurality of stochastic computing units to provide at least one weighted response and providing the at least one weighted response to a second stochastic computing unit of the portion of the plurality of stochastic computing units.

2. The system of claim 1 wherein at least one the programmable interconnect includes at least one field programmable gate array (FPGA).

3. The system of claim 2 wherein the plurality of nodes are fully connected through the multiplication unit.

4. The system of claim 3 wherein the at least one multiplication unit includes a crossbar array.

5. The system of claim 2 , wherein the at least one multiplication unit is programmable.

6. The system of claim 5 , wherein the plurality of nodes are sparsely connected through the at least one multiplication unit.

7. The system of claim 5 , wherein the at least one multiplication unit includes at least one additional FPGA.

8. The system of claim 2 , wherein each of the plurality of nodes operate at not less than zero degrees Celsius.

9. The system of claim 1 , wherein the digital representation of the analog oscillator is configured to solve governing differential equations for the analog oscillator and wherein the analog oscillator is an inductor-capacitor oscillator.

10. The system of claim 1 , further comprising:

at least one of a central processing unit coupled with the OPU and a graphics processing unit coupled with the OPU.

11. A system, comprising:

at least one processor; and

an optimization processing unit (OPU) coupled with the at least one processor, the OPU including a plurality of stochastic computing units and at least field programmable gate array (FPGA), each of the plurality of stochastic computing units including a plurality of nodes and at least one multiplication unit configured to interconnect at least a portion of the plurality of nodes, each of the plurality of nodes corresponding to an oscillator, the at least one multiplication unit being configured to multiply an output sampled from a node of the plurality of nodes with a corresponding weight, the FPGA being configured to provide weights for and to selectably couple a portion of the plurality of stochastic computing units;

wherein the oscillator is selected from an analog oscillator and a digital representation of the analog oscillator.

12. A method, comprising:

receiving, at an optimization processing unit (OPU), data for at least a portion of an optimization problem, the OPU including a plurality of stochastic computing units and at least one programmable interconnect, each of the plurality of stochastic computing units including a plurality of nodes and at least one multiplication unit configured to interconnect at least a portion of the plurality of nodes, each of the plurality of nodes including an oscillator selected from an analog oscillator and a digital representation of the analog oscillator, the multiplication unit multiplying an output from a node of the at least the portion of the plurality of nodes by a weight to provide a weighted output and providing the weighted output to an input of at least one other node of the at least the portion of the plurality of nodes;

calculating, in the plurality of stochastic computing units, a plurality of responses for the at least the portion of the optimization problem;

applying, by the at least one programmable interconnect, a plurality of weights to the plurality of responses from the plurality of stochastic computing units to provide a plurality of weighted responses; and

providing, by the at least one programmable interconnect, at least one of the plurality of weighted responses for each of the plurality of stochastic computing units as at least one input to each stochastic computing unit of a portion of the plurality of stochastic computing units.

13. The method of claim 12 wherein at least one the programmable interconnect includes at least one field programmable gate array (FPGA).

14. The method of claim 12 , wherein each of the plurality of nodes operate at not less than zero degrees Celsius.

15. The method of claim 12 , wherein the calculating further includes:

calculating the plurality of responses in parallel in the plurality of stochastic computing units.

16. The method of claim 12 , wherein the receiving further includes:

receiving, at the OPU, the at least the portion of the data for the optimization problem from at least one of a central processing unit coupled with the OPU and a graphics processing unit coupled with the OPU.