Transistor structure with reduced leakage current and adjustable on/off current
View Patent ↗A transistor structure includes a gate, a spacer, a channel region, a first concave, and a first conductive region. The gate is above a silicon surface. The spacer is above the silicon surface and at least covers a sidewall of the gate. The channel region is under the silicon surface. The first conductive region is at least partially formed in the first concave, wherein a conductive region of a neighborhood transistor structure next to the transistor structure is at least partially formed in the first concave.
1. A transistor structure comprising:
a gate above a semiconductor surface;
a spacer above the semiconductor surface and covering a sidewall of the gate;
a channel region, wherein at least part of the channel region is under the gate;
a first conductive region extending upward and a top surface of the first conductive region being higher than the semiconductor surface, wherein the first conductive region is on a first insulation layer, a part of a sidewall of the first conductive region is covered by a part of a second insulation layer and a part of a sidewall of a conductive region of a neighborhood transistor structure is covered by another part of the second insulation layer, and the second insulation layer does not extend from the sidewall of the first conductive region to the sidewall of the second conductive region of the neighborhood transistor structure; and
a second conductive region extending upward and a top surface of the second conductive region being higher than the semiconductor surface, wherein the first insulation layer does not extend under the gate.
2. The transistor structure in claim 1 , wherein the transistor structure is an asymmetric transistor, a first doping concentration profile of the first conductive region along a first extension direction is different from a second doping concentration profile of the second conductive region along a second extension direction.
3. The transistor structure in claim 1 , wherein the transistor structure is an asymmetric transistor, a structure among the gate and the first conductive region is different from a structure between the gate and the second conductive region.
4. The transistor structure in claim 3 , wherein an LDD zone is formed between the gate and the first conductive region.
5. The transistor structure in claim 1 , wherein the transistor structure is an asymmetric transistor, the first conductive region comprises a first lower part under the semiconductor surface and the second conductive region comprises a second lower part under the semiconductor surface, and a thickness of the first lower part is different from a thickness of the second lower part.
6. The transistor structure in claim 1 , wherein the transistor structure is an asymmetric transistor, a width of one terminal of the channel region next to the first conductive region is different from a width of another terminal of the channel region next to the second conductive region.
7. The transistor structure in claim 1 , wherein the transistor structure is an asymmetric transistor, a material of the first conductive region is different from a material of the second conductive region.
8. A transistor structure comprising:
a substrate with a semiconductor surface;
a gate above the semiconductor surface;
a spacer above the semiconductor surface and covering a sidewall of the gate;
a channel region, wherein at least part of the channel region is under the gate;
a first conductive region extending upward and a top surface of the first conductive region being higher than the semiconductor surface, wherein one side of the first conductive region abuts against the spacer, and another side opposite to the one side abuts against an insulation layer; and
a second conductive region extending upward and a top surface of the second conductive region being higher than the semiconductor surface;
wherein a metal plug contacts to a top side of the first conductive region and the another side of the first conductive region, and at least part of the metal plug is lower than the semiconductor surface.
9. The transistor structure in claim 8 , wherein the transistor structure is an asymmetric transistor, a first doping concentration profile of the first conductive region along a first extension direction is different from a second doping concentration profile of the second conductive region along a second extension direction.
10. The transistor structure in claim 8 , wherein the transistor structure is an asymmetric transistor, a structure among the gate and the first conductive region is different from a structure between the gate and the second conductive region.
11. The transistor structure in claim 10 , wherein an LDD zone is formed between the gate and the first conductive region.
12. The transistor structure in claim 8 , wherein the transistor structure is an asymmetric transistor, the first conductive region comprises a first lower part under the semiconductor surface and the second conductive region comprises a second lower part under the semiconductor surface, and a thickness of the first lower part is different from a thickness of the second lower part.
13. The transistor structure in claim 8 , wherein the transistor structure is an asymmetric transistor, a width of one terminal of the channel region next to the first conductive region is different from a width of another terminal of the channel region next to the second conductive region.
14. The transistor structure in claim 8 , wherein the transistor structure is an asymmetric transistor, a material of the first conductive region is different from a material of the second conductive region.
15. A transistor structure comprising:
a semiconductor substrate with a semiconductor surface;
a gate above the semiconductor surface;
a spacer above the semiconductor surface and covering a sidewall of the gate;
a channel region, wherein at least part of the channel region is under the gate;
a concave under the semiconductor surface, and an opening above the concave and above the semiconductor surface and next to the spacer;
a first conductive region extending upward, wherein the first conductive region is on a first insulation layer and the first insulation layer is formed in the concave; and
a metal plug filled in the concave and the opening above the concave, and the metal plug contacts to two sides of the first conductive region.
16. The transistor structure in claim 15 , wherein the transistor structure is an asymmetric transistor, a first doping concentration profile of the first conductive region along a first extension direction is different from a second doping concentration profile of the second conductive region along a second extension direction.
17. The transistor structure in claim 15 , wherein the transistor structure is an asymmetric transistor, a structure among the gate and the first conductive region is different from a structure between the gate and the second conductive region.
18. The transistor structure in claim 15 , wherein the transistor structure is an asymmetric transistor, the first conductive region comprises a first lower part under the silicon surface and the second conductive region comprises a second lower part under the silicon surface, and a thickness of the first lower part is different from a thickness of the second lower part.
19. The transistor structure in claim 15 , wherein the transistor structure is an asymmetric transistor, a width of one terminal of the channel region next to the first conductive region is different from a width of another terminal of the channel region next to the second conductive region.
20. The transistor structure in claim 15 , wherein the transistor structure is an asymmetric transistor, a material of the first conductive region is different from a material of the second conductive region.