Method of controlling on-die termination and system performing the same
A method of controlling on-die termination (ODT) in a multi-rank system including a plurality of memory ranks is provided. The method includes: enabling ODT circuits of the plurality of memory ranks into an initial state when the multi-rank system is powered on; enabling the ODT circuits of a write target memory rank and non-target memory ranks among the plurality of memory ranks during a write operation; and disabling the ODT circuit of a read target memory rank among the plurality of memory ranks while enabling the ODT circuits of non-target memory ranks among the plurality of memory ranks during a read operation.
1. A method of operating a dynamic random access memory (DRAM) in a multi-rank memory system, the multi-rank memory system including a first rank and a second rank, the first rank being enabled by a first rank selection signal and the second rank being enabled by a second rank selection signal respectively, the method comprising:
setting a mode register set to enable one of first on-die-termination (ODT) operation mode and second on-die-termination (ODT) operation mode;
receiving a first CAS command and a write command consecutively in synchronization with an operation clock signal pair from an external device through a command bus shared by the first and second ranks while the first rank selection signal is being enabled and the second rank selection signal is being disabled;
receiving a write data from the external device through a data bus shared by the first and second ranks after receiving the first CAS command and the write command, wherein, when the first ODT operation mode is enabled, a first ODT circuit of the first rank and a second ODT circuit of the second rank are enabled respectively while receiving the write data, and when the second ODT operation mode is enabled, the first ODT circuit of the first rank is enabled and the second ODT circuit of the second rank is disabled while receiving the write data;
receiving a data strobe signal pair while receiving the write data, the data strobe signal pair toggles in synchronization with the operation clock signal pair, wherein toggling frequency of the data strobe signal pair is higher than a frequency of the operation clock signal pair;
receiving a second CAS command and a read command consecutively through the command bus while the first rank selection signal is being enabled and the second rank selection signal is being disabled; and
outputting a read data through the data bus in response to the second CAS command and the read command, wherein, when the first ODT operation mode is enabled, the first ODT circuit of the first rank is disabled and the second ODT circuit of the second rank is enabled respectively while outputting the read data, and when the second ODT operation mode is enabled, the first ODT circuit of the first rank and the second ODT circuit of the second rank are disabled respectively while outputting the read data.
2. The method of claim 1 , wherein the toggling frequency of the data strobe signal pair is twice higher than the frequency of the operation clock signal pair.
3. The method of claim 1 , wherein the toggling frequency of the data strobe signal pair is four times higher than the frequency of the operation clock signal pair.
4. The method of claim 1 , wherein the first CAS command includes a first field which indicates that the write command is immediately followed, and the logic level of the first field is high.
5. The method of claim 1 , wherein the second CAS command includes a second field which indicates that the read command is immediately followed, and the logic level of the second field is high.
6. The method of claim 1 , further setting a second mode register to set a first resistance value of the first ODT circuit and to set a second resistance value of the second ODT circuit.
7. The method of claim 1 , wherein the first memory rank is a target memory rank and the second memory rank is a non-target memory rank, and the DRAM in the target memory rank performs write and read operations in response to the write and read commands.
8. The method of claim 1 , wherein, when the DRAM is powered-on, default setting of the mode register set is the first ODT operation mode.
9. The method of claim 8 , wherein an ODT operation mode transitioning from the first ODT operation mode to the second ODT operation mode is accomplished by a mode register set programming procedure.
10. The method of claim 1 , wherein an ODT resistance of the first ODT circuit is set to have a first value during the first ODT operation mode and a second value during the second ODT operation mode respectively, and the first value is different from the second value.
11. The method of claim 10 , wherein the first value and second value are selected from several different resistance values stored in a second mode register set.
12. A multi-rank memory system, the multi-rank memory system comprising:
a mode register set configured to enable one of first on-die-termination (ODT) operation mode and second on-die-termination (ODT) operation mode;
a first rank including a first dynamic random access memory (DRAM), the first DRAM being enabled by a first rank selection signal;
a second rank including a second dynamic random access memory (DRAM), the second DRAM being enabled by a second rank selection signal;
an operation clock bus providing the first rank and the second rank with an operation clock signal pair;
a command bus shared by the first rank and the second rank and connected to an external device;
a data bus shared by the first rank and the second rank and connected to the external device; and
a data strobe bus shared by the first rank and the second rank and connected to the external device;
wherein the first DRAM configured to:
receive a first CAS command and a write command consecutively in synchronization with the operation clock signal pair through the command bus while the first rank selection signal is being enabled and the second rank selection signal is being disabled;
receive a write data through the data bus after receiving the first CAS command and the write command, and when the first ODT operation mode is enabled, a first ODT circuit of the first rank and a second ODT circuit of the second rank are enabled respectively while receiving the write data, and when the second ODT operation mode is enabled, the first ODT circuit of the first rank is enabled and the second ODT circuit of the second rank is disabled while receiving the write data;
receive a data strobe signal pair while receiving the write data, the data strobe signal pair toggles in synchronization with the operation clock signal pair, and toggling frequency of the data strobe signal pair is higher than a frequency of the operation clock signal pair;
receive a second CAS command and a read command consecutively through the command bus while the first rank selection signal is being enabled and the second rank selection signal is being disabled; and
output a read data through the data bus in response to the second CAS command and the read command, and when the first ODT operation mode is enabled, the first ODT circuit of the first rank is disabled and the second ODT circuit of the second rank is enabled respectively while outputting the read data, and when the second ODT operation mode is enabled, the first ODT circuit of the first rank and the second ODT circuit of the second rank are disabled respectively while outputting the read data.
13. The multi-rank memory system of claim 12 , wherein the toggling frequency of the data strobe signal pair is twice higher than the frequency of the operation clock signal pair.
14. The multi-rank memory system of claim 12 , wherein the first CAS command includes a first field which indicates that the write command is immediately followed, and the logic level of the first field is high.
15. The multi-rank memory system of claim 12 , wherein the second CAS command includes a second field which indicates that the read command is immediately followed, and the logic level of the second field is high.
16. The multi-rank memory system of claim 12 , further setting a second mode register to set a first resistance value of the first ODT circuit and to set a second resistance value of the second ODT circuit.
17. The multi-rank memory system of claim 12 , wherein the first memory rank is a target memory rank and the second memory rank is a non-target memory rank, and the DRAM in the target memory rank performs write and read operations in response to the write and read commands.
18. The multi-rank memory system of claim 12 , wherein, when the DRAM is powered-on, default setting of the mode register set is the first ODT operation mode.
19. The multi-rank memory system of claim 18 , wherein an ODT operation mode transitioning from the first ODT operation mode to the second ODT operation mode is accomplished by mode register set programming procedure.
20. The multi-rank memory system of claim 12 , wherein an ODT resistance of the first ODT circuit is set to have a first value during the first ODT operation mode and a second value during the second ODT operation mode respectively, and the first value is different from the second value.