System and method for I/O aware processor configuration
An information handling system includes an I/O device, a first processor die coupled to the I/O device, a second processor die coupled to the first processor die, and to no I/O device, and boot process logic. The boot process logic determines that the first processor die is coupled to the I/O device and that the second processor die is coupled to no I/O device, determines that an operating environment of the information handling system is capable of utilizing a maximum of Z processor cores, where Z is an integer number that is greater than X and less than the sum of X+Y, and enables Z processor cores on the first and second processor dies by enabling the X processor cores on the first processor die, and enabling the remainder of cores, equal to Z−X, on the second processor die, based upon the determination that the second processor die is coupled to no I/O device.
1. An information handling system, comprising:
a first processor including a first memory channel to which a first memory device is coupled, and a first input/output (I/O) channel to which a first I/O device is coupled;
a second processor including a second memory channel to which a second memory device is coupled, and a second I/O channel to which a second I/O device is coupled;
a third processor including a third memory channel to which a third memory device is coupled, and a third I/O channel to which a third I/O device is coupled;
a fourth processor including a fourth memory channel to which a fourth memory device is coupled, and a fourth I/O channel to which a fourth I/O device is coupled; and
operating code configured to:
set the information handling system into a maximum performance level mode;
place the first processor into a first non-uniform memory access (NUMA) proximity domain, the second processor into a second NUMA proximity domain, the third processor into a third NUMA proximity domain, and the fourth processor into a fourth NUMA proximity domain in response to setting the information handling system into the maximum performance level mode;
set the information handling system into a maximum performance level per watt mode; and
place the first and second processors into a fifth NUMA proximity domain, and the third and fourth processor into a fifth NUMA proximity domain in response to setting the information handling system into the maximum performance level per watt mode.
2. The information handling system of claim 1 , wherein the operating code is further configured, in the maximum performance mode, to load each one of a plurality of processes onto a selected one of the first, second, third, and fourth NUMA proximity domains, wherein each process utilizes a particular one of the first, second, third, or fourth I/O device more than the other I/O devices, and wherein the selected NUMA proximity domain for each process includes the associated particular I/O device.
3. The information handling system of claim 2 , wherein the operating code is further configured, in the maximum performance per Watt mode, to load each one of the processes onto a selected one of the fifth and sixth NUMA proximity domains such that the fifth NUMA proximity domain is loaded first, and then, when no more processes can be loaded onto the fifth NUMA proximity domain, then the processes are loaded onto the sixth NUMA proximity domain.
4. The information handling system of claim 3 , wherein the operating code comprises one of a system Basic Input/Output System (BIOS), a Unified Extensible Firmware Interface (UEFI), an Operating System (OS), and an application.
5. The information handling system of claim 1 , wherein the first, second, third, and fourth processors are coupled together via coherent fabric links.
6. The information handling system of claim 5 , wherein the coherent fabric links comprise Global Memory Interconnect (GMI) fabric links.
7. The information handling system of claim 1 , wherein the first processor is coupled to the first I/O device via a serial data interface.
8. The information handling system of claim 7 , wherein the serial data interface comprises a x16 Peripheral Component Interconnect-Express (PCIe) interface.
9. A method, comprising:
coupling a first processor to a first memory device and to a first input/output (I/O) device;
coupling a second processor to a second memory device and to a second I/O device;
coupling a third processor to a third memory device and to a third I/O device;
coupling a fourth processor to a fourth memory device and to a fourth I/O device;
setting the information handling system into a maximum performance level mode;
placing the first processor into a first non-uniform memory access (NUMA) proximity domain, the second processor into a second NUMA proximity domain, the third processor into a third NUMA proximity domain, and the fourth processor into a fourth NUMA proximity domain in response to setting the information handling system into the maximum performance level mode;
setting the information handling system into a maximum performance level per watt mode; and
placing the first and second processors into a fifth NUMA proximity domain, and the third and fourth processor into a fifth NUMA proximity domain in response to setting the information handling system into the maximum performance level per watt mode.
10. The method of claim 9 , further comprising:
loading, in the maximum performance mode, each one of a plurality of processes onto a selected one of the first, second, third, and fourth NUMA proximity domains, wherein each process utilizes a particular one of the first, second, third, or fourth I/O device more than the other I/O devices, and wherein the selected NUMA proximity domain for each process includes the associated particular I/O device.
11. The method of claim 10 , further comprising:
loading, in the maximum performance per Watt mode, each one of the processes onto a selected one of the fifth and sixth NUMA proximity domains such that the fifth NUMA proximity domain is loaded first, and then, when no more processes can be loaded onto the fifth NUMA proximity domain, then the processes are loaded onto the sixth NUMA proximity domain.
12. The method of claim 11 , wherein the operating code comprises one of a system Basic Input/Output System (BIOS), a Unified Extensible Firmware Interface (UEFI), an Operating System (OS), and an application.
13. The information handling system of claim 9 , further comprising:
coupling the first, second, third, and fourth processors together via coherent fabric links.
14. The information handling system of claim 13 , wherein the coherent fabric links comprise Global Memory Interconnect (GMI) fabric links.
15. The information handling system of claim 9 , further comprising:
coupling the first processor to the first I/O device via a serial data interface.
16. The information handling system of claim 15 , wherein the serial data interface comprises a x16 Peripheral Component Interconnect-Express (PCIe) interface.
17. An information handling system, comprising:
a first processor including a first memory channel to which a first memory device is coupled, and a first serial data interface to which a first I/O device is coupled;
a second processor including a second memory channel to which a second memory device is coupled, and a second serial data interface to which a second I/O device is coupled, wherein the second processor is coupled to the first processor via a first coherent fabric link;
a third processor including a third memory channel to which a third memory device is coupled, and a third serial data interface to which a third I/O device is coupled, wherein the third processor is coupled to the second processor via a first coherent fabric link;
a fourth processor including a fourth memory channel to which a fourth memory device is coupled, and a fourth serial data interface to which a fourth I/O device is coupled, wherein the fourth processor is coupled to the third processor via a third coherent fabric link and to the first processor via a fourth coherent fabric link; and
operating code configured to:
set the information handling system into a maximum performance level mode;
place the first processor into a first non-uniform memory access (NUMA) proximity domain, the second processor into a second NUMA proximity domain, the third processor into a third NUMA proximity domain, and the fourth processor into a fourth NUMA proximity domain in response to setting the information handling system into the maximum performance level mode;
set the information handling system into a maximum performance level per watt mode; and
place the first and second processors into a fifth NUMA proximity domain, and the third and fourth processor into a fifth NUMA proximity domain in response to setting the information handling system into the maximum performance level per watt mode.
18. The information handling system of claim 17 , wherein the operating code is further configured, in the maximum performance mode, to load each one of a plurality of processes onto a selected one of the first, second, third, and fourth NUMA proximity domains, wherein each process utilizes a particular one of the first, second, third, or fourth I/O device more than the other I/O devices, and wherein the selected NUMA proximity domain for each process includes the associated particular I/O device.
19. The information handling system of claim 18 , wherein the operating code is further configured, in the maximum performance per Watt mode, to load each one of the processes onto a selected one of the fifth and sixth NUMA proximity domains such that the fifth NUMA proximity domain is loaded first, and then, when no more processes can be loaded onto the fifth NUMA proximity domain, then the processes are loaded onto the sixth NUMA proximity domain.
20. The information handling system of claim 19 , wherein the operating code comprises one of a system Basic Input/Output System (BIOS), a Unified Extensible Firmware Interface (UEFI), an Operating System (OS), and an application.