Chip package structure
A chip package structure including first and second insulating layers, first and second circuit structures, a chip on the first circuit structure, an encapsulant, a conductive through via, and first and second heat dissipation layers is provided. The first circuit structure is disposed at the first surface of the first insulating layer. The bottom electrode of the chip is electrically connected to the first circuit structure. The second circuit structure is disposed on the chip and electrically connected to the top electrode of the chip. The encapsulant encapsulates the first and second circuit structures and the chip. The conductive through via is disposed in the encapsulant and connects the first and second circuit structures. The second insulating layer is disposed on the second circuit structure. The first heat dissipation layer is disposed on the first insulating layer. The second heat dissipation layer is disposed on the second insulating layer.
1. A chip package structure, comprising:
a first insulating layer having a first surface and a second surface opposite to each other;
a first circuit structure disposed at the first surface;
a first chip disposed on the first circuit structure, wherein the first chip has a top electrode and a bottom electrode, and the bottom electrode is electrically connected to the first circuit structure;
a second circuit structure disposed on the first chip and electrically connected to the top electrode;
an encapsulant disposed on the first insulating layer and encapsulating the first circuit structure, the first chip, and the second circuit structure;
a conductive through via disposed in the encapsulant and connected to the first circuit structure and the second circuit structure;
a second insulating layer disposed on the second circuit structure;
a first heat dissipation layer disposed on the second surface; and
a second heat dissipation layer disposed on the second insulating layer,
wherein the first heat dissipation layer and the second heat dissipation layer are electrically insulated from the first chip.
2. The chip package structure of claim 1 , wherein the first chip comprises a power chip.
3. The chip package structure of claim 1 , further comprising a third circuit structure disposed on the second surface and electrically insulated from the first heat dissipation layer, wherein the conductive through via is disposed in the encapsulant and the first insulating layer and connected to the first circuit structure, the second circuit structure, and the third circuit structure.
4. The chip package structure of claim 1 , further comprising a fourth circuit structure disposed on the second insulating layer and electrically insulated from the second heat dissipation layer, wherein the conductive through via is disposed in the encapsulant and the second insulating layer and connected to the first circuit structure, the second circuit structure, and the fourth circuit structure.
5. The chip package structure of claim 1 , further comprising a third circuit structure and a fourth circuit structure, the third circuit structure is disposed on the second surface and electrically insulated from the first heat dissipation layer, and the fourth circuit structure is disposed on the second insulating layer and electrically insulated from the second heat dissipation layer, wherein the conductive through via is disposed in the encapsulant, the first insulating layer, and the second insulating layer and connected to the first circuit structure, the second circuit structure, the third circuit structure, and the fourth circuit structure.
6. The chip package structure of claim 5 , wherein an upper side and a lower side of the encapsulant have a symmetrical structure.
7. The chip package structure of claim 1 , wherein the second insulating layer exposes a portion of the second circuit structure.
8. The chip package structure of claim 1 , wherein the second insulating layer covers the entire second circuit structure.
9. The chip package structure of claim 1 , further comprising a second chip disposed on the first circuit structure, the second chip has a top electrode, and the top electrode and the second circuit structure are electrically connected.
10. The chip package structure of claim 9 , wherein the second chip does not comprise a power chip.
11. The chip package structure of claim 9 , wherein the top electrode of the second chip is directly connected to the second circuit structure.
12. The chip package structure of claim 1 , wherein the bottom electrode of the first chip is directly connected to the first circuit structure.
13. The chip package structure of claim 1 , wherein the top electrode of the first chip is directly connected to the second circuit structure.
14. The chip package structure of claim 1 , further comprising a circuit board disposed between the first circuit structure and the second circuit structure, wherein the first chip is located in a groove of the circuit board, and an insulating layer completely fills the groove.
15. The chip package structure of claim 1 , wherein the first heat dissipation layer comprises a metal layer.
16. The chip package structure of claim 1 , wherein the second heat dissipation layer comprises a metal layer.
17. A chip package structure, comprising:
a first insulating layer having a first surface and a second surface opposite to each other;
a first circuit structure disposed at the first surface;
a first chip disposed on the first circuit structure, wherein the first chip has a top electrode and a bottom electrode, and the bottom electrode is electrically connected to the first circuit structure;
a second circuit structure disposed on the first chip and electrically connected to the top electrode;
an encapsulant disposed on the first insulating layer and encapsulating the first circuit structure, the first chip, and the second circuit structure;
a conductive through via disposed in the encapsulant and connected to the first circuit structure and the second circuit structure;
a second insulating layer disposed on the second circuit structure;
a first heat dissipation layer disposed on the second surface;
a second heat dissipation layer disposed on the second insulating layer; and
a third circuit structure disposed on the second surface and electrically insulated from the first heat dissipation layer, wherein the conductive through via is disposed in the encapsulant and the first insulating layer and connected to the first circuit structure, the second circuit structure and the third circuit structure.
18. A chip package structure, comprising:
a first insulating layer having a first surface and a second surface opposite to each other;
a first circuit structure disposed at the first surface;
a first chip disposed on the first circuit structure, wherein the first chip has a top electrode and a bottom electrode, and the bottom electrode is electrically connected to the first circuit structure;
a second circuit structure disposed on the first chip and electrically connected to the top electrode;
an encapsulant disposed on the first insulating layer and encapsulating the first circuit structure, the first chip, and the second circuit structure;
a conductive through via disposed in the encapsulant and connected to the first circuit structure and the second circuit structure;
a second insulating layer disposed on the second circuit structure;
a first heat dissipation layer disposed on the second surface;
a second heat dissipation layer disposed on the second insulating layer; and
a fourth circuit structure disposed on the second insulating layer and electrically insulated from the second heat dissipation layer, wherein the conductive through via is disposed in the encapsulant and the second insulating layer and connected to the first circuit structure, the second circuit structure and the fourth circuit structure.
19. A chip package structure, comprising:
a first insulating layer having a first surface and a second surface opposite to each other;
a first circuit structure disposed at the first surface;
a first chip disposed on the first circuit structure, wherein the first chip has a top electrode and a bottom electrode, and the bottom electrode is electrically connected to the first circuit structure;
a second circuit structure disposed on the first chip and electrically connected to the top electrode;
an encapsulant disposed on the first insulating layer and encapsulating the first circuit structure, the first chip, and the second circuit structure;
a conductive through via disposed in the encapsulant and connected to the first circuit structure and the second circuit structure;
a second insulating layer disposed on the second circuit structure;
a first heat dissipation layer disposed on the second surface;
a second heat dissipation layer disposed on the second insulating layer; and
a second chip disposed on the first circuit structure, wherein the second chip has a top electrode, and the top electrode and the second circuit structure are electrically connected.