Screening method for pin diodes used in microwave limiters
A method of testing a PIN diode for a power limiter circuit comprises measuring a reverse bias current of the PIN diode; applying a reverse bias voltage to the PIN diode; increasing the reverse bias voltage until the reverse bias current of the PIN diode reaches a threshold current indicative of a reverse voltage breakdown; and determining whether the reverse bias breakdown voltage of the PIN diode is within an acceptable range of reverse bias breakdown voltages corresponding to a power range at which the power limiter circuit would enter power limiting mode with the PIN diode.
1. A method of testing a PIN diode for a power limiter circuit, the method comprising:
measuring a reverse bias current of the PIN diode;
applying a reverse bias voltage to the PIN diode;
increasing the reverse bias voltage until the reverse bias current of the PIN diode reaches a threshold current indicative of a reverse bias voltage breakdown; and
determining whether the reverse bias breakdown voltage of the PIN diode is within an acceptable range of reverse bias breakdown voltages corresponding to a power range at which the power limiter circuit would enter power limiting mode with the PIN diode.
2. The method of claim 1 , wherein the acceptable range of reverse bias breakdown voltages is associated with a forward bias voltage rating of the PIN diode.
3. The method of claim 1 , wherein the threshold current is at least around 10 microamps.
4. The method of claim 1 , wherein the acceptable range of reverse bias breakdown voltages is associated with a forward bias resistance rating.
5. The method of claim 1 , wherein the PIN diode is a select PIN diode, further comprising—
selecting from a group of PIN diodes a first group of test PIN diodes;
measuring a reverse bias breakdown voltage for each of the first group of test PIN diodes;
connecting each of the first group of test PIN diodes into corresponding power limiter circuits;
measuring a power at which each of the corresponding power limiter circuits enter power limiting mode; and
determining the acceptable range of reverse bias breakdown voltages based on the power at which each of the corresponding power limiter circuits entered power limiting mode.
6. The method of claim 5 , wherein the power limiter circuits comprise a DC block and an RF choke.
7. The method of claim 6 , wherein the RF choke comprises an inductor.
8. The method of claim 6 , wherein the DC block comprises a capacitor.
9. The method of claim 5 , wherein the acceptable range of reverse bias breakdown voltages is at least partially based on a correlation between the reverse bias breakdown voltages of the first group of test PIN diodes and the power at which each of the corresponding power limiter circuits entered power limiting mode.
10. The method of claim 9 , wherein the correlation comprises a correlation coefficient of at least about 0.5.
11. The method of claim 9 , wherein the acceptable range of reverse bias breakdown voltages is at least partially based on the correlation and an acceptable range of powers at which each of the corresponding power limiter circuits entered power limiting mode.
12. The method of claim 5 , wherein the select PIN diode is configured to enter an on state when the power limiter circuit enters power limiting mode.
13. The method of claim 1 , wherein the reverse bias voltage breakdown is determined using a curve tracer.
14. A method of testing a PIN diode for a power limiter circuit, the method comprising:
determining an acceptable range of reverse bias breakdown voltages of the PIN diode based on a power at which a test power limiter circuit comprising a test PIN diode enters power limiting mode and a reverse bias breakdown voltage of the test PIN diode;
measuring a reverse bias breakdown voltage of the PIN diode; and
determining whether the reverse bias breakdown voltage of the PIN diode is within the acceptable range of reverse bias breakdown voltages.
15. The method of claim 14 , further comprising deriving the acceptable range of reverse bias breakdown voltages based at least in part on a correlation between a reverse bias breakdown voltage of the test PIN diode and the power at which the test power limiter circuit enters power limiting mode.
16. The method of claim 14 , wherein a forward bias voltage rating of the test PIN diode is the same as a forward bias voltage rating of the PIN diode.
17. A method of testing a select PIN diode for a power limiter circuit, the method comprising:
selecting from a group of PIN diodes a plurality of test PIN diodes;
measuring a reverse bias breakdown voltage for each of the test PIN diodes;
incorporating each of the test PIN diodes into corresponding power limiter circuits;
measuring a power at which each of the corresponding power limiter circuits enters power limiting mode;
determining an acceptable range of reverse bias breakdown voltages based on the power at which each of the corresponding power limiter circuits entered power limiting mode;
measuring a reverse bias breakdown voltage of the select PIN diode; and
determining whether the reverse bias breakdown voltage of the select PIN diode is within the acceptable range of reverse bias breakdown voltages.
18. The method of claim 17 , wherein the power limiter circuits each comprise a pair of DC blocks in series with one another and an RF choke.
19. The method of claim 18 , wherein the RF choke comprises an inductor.
20. The method of claim 18 , wherein the DC blocks comprise capacitors.