Multi-addressing mode for DMA and non-sequential read and write patterns
Examples herein describe performing non-sequential DMA read and writes. Rather than storing data sequentially, a DMA engine can write data into memory using non-sequential memory addresses. A data processing engine (DPE) controller can submit a first job using first parameters that instruct the DMA engine to store data using a first non-sequential write pattern. The DPE controller can also submit a second job using second parameters that instruct the DMA engine to store data using a second, different non-sequential write pattern. In this manner, the DMA engine can switch to performing DMA writes using different non-sequential patterns. Similarly, the DMA engine can use non-sequential reads to retrieve data from memory. When performing a first DMA read, the DMA engine can retrieve data from memory using a first sequential pattern and then perform a second DMA read where data is retrieved from memory using a second non-sequential read pattern.
1. An integrated circuit (IC), comprising:
a switch;
a direct memory access (DMA) engine comprising multiple reconfigurable buffer descriptors configured with respective address generation parameters; and
a memory;
wherein the DMA engine is configured to:
receive data from the switch,
select a first one of the buffer descriptors for a first DMA write request based on a first instruction received by the DMA engine, and
write the data to the memory in a first non-sequential write pattern based on the address generation parameters of the first buffer descriptor.
2. The IC of claim 1 , wherein the memory comprises memory banks, wherein the DMA engine generates a first memory address for a first one of memory banks to store a first data chunk and generates a second memory address for a second one of the memory banks to store a second data chunk, wherein the first and second data chunks are sequentially received from the switch.
3. The IC of claim 1 , wherein the DMA engine is further configured to:
receive subsequent data from the switch;
select a second one of the buffer descriptors based on a second instruction received by the DMA engine; and
write the subsequent data to the memory in a second non-sequential write pattern based on the address generation parameters of the second buffer descriptor.
4. The IC of claim 1 , wherein the first non-sequential write pattern results in the DMA engine performing a matrix function.
5. The IC of claim 4 , wherein the matrix function is one of: transposing matrix data received from the switch and storing a sub-portion of a matrix defined by the matrix data received from the switch.
6. The IC of claim 1 , wherein the first non-sequential write pattern results in the DMA engine de-interleaving the data as the DMA engine writes the data to the memory.
7. The IC of claim 1 , further comprising:
controller circuitry configured to replace the address generation parameters of one or more of the buffer descriptors during runtime.
8. A system on a chip (SoC), comprising:
a direct memory access (DMA) engine comprising multiple reconfigurable buffer descriptors (BDs) configured with respective address generation parameters; and
memory;
wherein the DMA engine is configured to:
receive a first DMA read request,
select a first one of the BDs based on a first instruction received by the DMA engine, and
read a first pattern of non-sequential addresses of the memory based on the address generation parameters of the first BD.
9. The SoC of claim 8 , wherein the memory comprises memory banks, wherein the DMA engine generates a first memory address for a first one of memory banks to retrieve a first data chunk and generates a second memory address for a second one of the memory banks to retrieve a second data chunk, and wherein the first and second data chunks are sequentially retrieved by the DMA engine when reading the first pattern of non-sequential addresses.
10. The SoC of claim 8 , wherein the DMA engine generates a first memory address for a first memory bank of the memory to retrieve a first data chunk and generates a second memory address for the first memory bank to retrieve a second data chunk, wherein the first and second data chunks are sequentially retrieved by the DMA engine when reading the first pattern of non-sequential addresses of the memory, and wherein the first and second memory addresses are non-sequential memory addresses in the first memory bank.
11. The SoC of claim 8 , wherein the first non-sequential read pattern results in the DMA engine performing a first matrix function when reading the first pattern of non-sequential addresses of the memory.
12. The SoC of claim 8 , wherein the DMA engine is further configured to:
receive a second DMA read request;
select a second one of the BDs based on a second instruction received by the DMA engine; and
read a second pattern of non-sequential addresses of the memory based on the address generation parameters of the second BD;
wherein the first pattern of non-sequential addresses differs from the second pattern of non-sequential addresses.
13. The SoC of claim 12 , wherein the second non-sequential read pattern results in the DMA engine performing a second matrix function when reading the second pattern of non-sequential addresses of the memory, wherein the second matrix function differs from a first matrix function performed when reading the first pattern of non-sequential addresses of the memory.
14. The SoC of claim 8 , further comprising:
controller circuitry configured to replace the address generation parameters of one or more of the buffer descriptors during runtime.
15. A method, comprising:
configuring multiple buffer descriptors of a direct memory access (DMA) engine with respective address generation parameters;
receiving a first DMA write request;
selecting a first one of the buffer descriptors based on a first instruction received by the DMA engine; and
writing data to a memory in a first non-sequential write pattern based on the address generation parameters of the first buffer descriptor.
16. The method of claim 15 , further comprising:
receiving a second DMA write request;
selecting a second one of the buffer descriptors based on a second instruction received by the DMA engine; and
writing subsequent data to the memory in a second non-sequential write pattern based on the address generation parameters of the second buffer descriptor.
17. The method of claim 15 , wherein the writing comprises:
generating a first memory address for a first memory bank to store a first data chunk of a data stream based on the address generation parameters of the first buffer descriptor; and
generating a second memory address for a second memory bank to store a second data chunk of the data stream based on the address generation parameters of the first buffer descriptor.
18. The method of claim 15 , wherein the writing comprises:
generating a first memory address for a first memory bank to store a first data chunk of a data stream based on the address generation parameters of the first buffer descriptor; and
generating a second memory address for the first memory bank to store a second data chunk of the data stream based on the address generation parameters of the first buffer descriptor, wherein the first and second memory addresses are non-sequential memory addresses in the first memory bank.
19. The method of claim 15 , wherein the first non-sequential write pattern results in the DMA engine performing a first matrix function when performing the writing.
20. The method of claim 15 , wherein the non-sequential write pattern results in the DMA engine de-interleaving the data as the DMA engine writes the data to the memory.