Mission critical wireless communication link master gateway
A master gateway operable in a wireless system is provided. The master gateway includes a plurality of receivers configured to wirelessly communicate over the mission critical wireless link system with a plurality of devices; a processing circuitry coupled to the plurality of receivers; and a memory containing instructions that, when executed by the processing circuitry, configure the processing circuitry to at least control the operation of the plurality of receivers, such that at least one of the plurality of receivers is configured to receive a plurality of transmissions from the plurality of devices in succession wherein a guard time between transmissions is significantly smaller than a processing time of a receiver.
1. A master gateway operable in a wireless system, comprising:
a plurality of receivers configured to wirelessly communicate with a plurality of devices;
a processing circuitry coupled to the plurality of receivers; and
a memory containing instructions that, when executed by the processing circuitry, configure the processing circuitry to at least control the operation of the plurality of receivers, such that at least one of the plurality of receivers is configured to receive a plurality of transmissions from the plurality of devices in succession wherein a guard time between transmissions is substantially shorter than a processing delay of the transmissions by the at least one receiver.
2. The master gateway of claim 1 , wherein the wireless system is a mission critical wireless link system.
3. The master gateway of claim 1 , wherein the at least one of the plurality of receivers further comprises at least one of: an automatic gain control (AGC), a packet detector, an analog-to-digital converter, a CORDIC transform, a carrier frequency offset estimation and correction (CFO), and a maximum likelihood sequence estimation (MLSE).
4. The master gateway of claim 1 , wherein the at least one of the plurality of receivers is configured to receive GFSK modulated signals.
5. The master gateway of claim 1 , wherein the master gateway is configured to operate in an IO-Link Wireless network.
6. The master gateway of claim 1 , further comprising:
a time slot generator configured to generate at least one of: a time slot start signal, a clock, and a time slot end signal.
7. The master gateway of claim 6 , further comprising:
a synchronous modem controller configured to receive at least one signal from the time slot generator and a packet detect signal from a packet detector, operable to issue at least one control signal to at least one other sub-component within the at least one of the plurality of receivers.
8. The master gateway of claim 7 , wherein the synchronous modem controller issues the at least one control signal based on at least one of: a signal from said time slot generator, a timing protocol, and a packet detect signal.
9. A receiver configured to wirelessly receive packets from a plurality of devices, comprising;
a synchronous modem controller configured to control a receiver to receive a plurality of transmissions from a plurality of devices in succession, wherein a guard time between transmissions is substantially shorter than a processing delay of the receiver.
10. The receiver of claim 9 , wherein the receiver further comprises:
an automatic gain control (AGC), a packet detector, an analog-to-digital converter, a CORDIC transform, a carrier frequency offset estimation and correction (CFO), and a maximum likelihood sequence estimation (MLSE).
11. The receiver of claim 9 , wherein the receiver is configured to receive GFSK modulated signals.
12. The receiver of claim 9 , wherein the receiver is configured to operate in an IO-Link Wireless network.