Layout parasitics and device parameter prediction using graph neural networks
A graph neural network to predict net parasitics and device parameters by transforming circuit schematics into heterogeneous graphs and performing predictions on the graphs. The system may achieve an improved prediction rate and reduce simulation errors.
1. A system comprising:
graph generation logic to transform a circuit schematic into a graph;
a first graph neural network;
embedding logic to generate a node embedding for the graph by concatenating previously generated node embeddings with aggregated neighbor embeddings, and to group different edge types of the graph independently for processing by attention layers during aggregation of the neighbor embeddings;
a second graph neural network;
the second graph neural network trained to output a wider range of parasitic prediction values for the circuit schematic than the first graph neural network; and
a plurality of different self-attention layers corresponding to groups of different edge types.
2. The system of claim 1 , wherein the parasitic prediction values are capacitive parasitic predictions.
3. A system comprising:
logic to transform a circuit schematic into a heterogeneous graph;
the heterogeneous graph comprising device nodes representing devices in the circuit schematic and net nodes representing nets in the circuit schematic;
a plurality of graph neural networks each trained to transform the heterogeneous graph into a range of parasitic prediction values for the circuit schematic between a common base level and a different maximum level; and
a circuit schematic simulator configured to receive the parasitic predictions and the device parameter predictions from the graph neural networks.
4. The system of claim 3 , wherein the parasitic predictions are parasitic capacitance predictions.
5. The system of claim 3 , further comprising:
the graph neural networks further configured to transform edges the graph into parasitic resistance predictions.
6. The system of claim 3 , wherein:
the device nodes comprise transistor device nodes; and
the heterogeneous graph comprises a plurality of heterogeneous edge types between the transistor device nodes and the net nodes.
7. The system of claim 6 , wherein:
the heterogeneous edge types comprise net to transistor drain edges, net to transistor gate edges, transistor drain to net edges, and transistor gate to net edges.
8. The system of claim 3 , wherein:
the heterogeneous graph excludes edges between device nodes and power rails and device nodes and ground rails.
9. The system of claim 3 , wherein:
the graph neural networks are further configured to:
sum vectors for groups of multiple edges of the heterogeneous graph into individually weighted vectors;
apply a self-attention layer separately to the individually weighted vectors for each group;
combine outputs of the self-attention layers for groups representing a same edge type into an output vector; and
sum the output vectors into a unified vector.
10. The system of claim 9 , wherein:
the graph neural networks each form a node embedding for a next network layer by applying weights of the next layer to the unified vector.
11. A method comprising:
providing a circuit schematic as a heterogeneous graph input to a plurality of graph neural networks, each of the graph neural networks generating a different range of parasitic prediction values for the circuit schematic;
generating device node embeddings for the graph using a plurality of aggregation and attention layers;
generating net node embeddings for the graph using the plurality of aggregation and attention layers; and
wherein the attention layers are self-attention layers assigned to process different types of heterogeneous net nodes.
12. The method of claim 11 , wherein each range has a common base level.
13. The method of claim 11 , wherein the parasitic predictions are parasitic capacitance predictions.
14. The method of claim 11 , further comprising:
the graph neural networks transforming edges the graph into parasitic resistance predictions.
15. The method of claim 11 , wherein:
the device nodes comprise transistor device nodes; and
the heterogeneous graph comprises a plurality of heterogeneous edge types between the transistor device nodes and the net nodes.
16. The method of claim 15 , wherein:
the heterogeneous edge types comprise net to transistor drain edges, net to transistor gate edges, transistor drain to net edges, and transistor gate to net edges.
17. The method of claim 11 , wherein:
the graph neural networks further configured to:
sum vectors for groups of multiple edges of the heterogeneous graph into individually weighted vectors;
apply a self-attention layer separately to the individually weighted vectors for each group;
combine outputs of the self-attention layers for groups representing a same edge type into an output vector; and
sum the output vectors into a unified vector.