System and method for an external processor to access internal registers
View Patent ↗The disclosure provides a system and method for an external processor to access internal register. The internal register may be a register of a core networking device. The method includes: sending, by an external processor, a read request to a core networking device; responding, by the core networking device, to the read request; sending, by the external processor, a write request to the core networking device; and preparing, by the core networking device, a register status notification of a register embedded in the core networking device and sends the register status notification to the external processor in response to the write request. The read and write requests and the responses are in a layer 2 protocol (L2 protocol).
1. A method for accessing a register of a core networking device, comprising:
sending, by an external processor, a read request to a core networking device;
responding, by the core networking device, to the read request;
sending, by the external processor, a write request to the core networking device; and
preparing, by the core networking device, a register status notification of a register and sends the register status notification to the external processor in response to the write request;
acknowledging, by the external processor, the register status notification;
wherein the read and write requests and the register status notification are in a layer 2 protocol (L2 protocol).
2. The method as in claim 1 , wherein the external processor is implemented as a system on chip (SoC) or a microcontroller unit (MCU).
3. The method as in claim 1 , wherein the L2 protocol is implemented as an Ethernet protocol compatible packet format including:
a destination MAC address section;
a source MAC address section;
an Ether type section;
a header; and
a register access information section.
4. The method as in claim 3 , wherein the destination MAC address section takes up six bytes, the source MAC address section takes up six bytes, and the Ether type section takes up four bytes.
5. A networking system, comprising:
a core networking device having a register embedded therein; and
an external processor, connected with the core networking device through an Ethernet protocol;
wherein the external processor sends a read request to the core networking device, the core networking device responds to the read request, the external processor then sends a write request, the core networking device prepares a register status notification of the register and sends the register status notification to the external processor in response to the write request;
wherein the external processor further acknowledges to the register status notification;
wherein the read and write requests and the responses are in a layer 2 protocol (L2 protocol).
6. The networking system as in claim 5 , wherein the external processor is implemented as a system on chip (SoC) or a microcontroller unit (MCU).
7. The networking system as in claim 5 , wherein the L2 protocol is implemented as an Ethernet protocol compatible packet format including:
a destination MAC address section;
a source MAC address section;
an Ether type section;
a header; and
a register access information section.
8. The networking system as in claim 7 , wherein the destination MAC address section takes up six bytes, the source MAC address section takes up six bytes, and the Ether type section takes up four bytes.