Memory management method and apparatus
A disclosed example apparatus includes memory; and processor circuitry to: identify a lock-protected section of instructions in the memory; replace lock/unlock instructions with transactional lock acquire and transactional lock release instructions to form a transactional process; and execute the transactional process in a speculative execution.
1. An apparatus comprising:
an interface;
first computer executable instructions; and
processor circuitry to execute the first computer executable instructions to:
determine a target process exceeded a processor utilization threshold, the target process including second instructions;
determine an instruction count of the second instructions satisfies a second threshold;
identify a lock-protected section of the second instructions;
replace lock/unlock instructions of the lock-protected section of the second instructions with transactional lock acquire instructions and transactional lock release instructions, the transactional lock acquire instructions and the transactional lock release instructions to form a transactional process; and
execute the transactional process in a speculative execution.
2. The apparatus of claim 1 , wherein the processor circuitry is to execute the transactional process using lock elision.
3. The apparatus of claim 1 , wherein the processor circuitry includes transactional translation circuitry to identify the lock-protected section of the second instructions, replace the lock/unlock instructions, and execute the transactional process.
4. The apparatus of claim 1 , wherein the processor circuitry is to roll back the transactional process if a conflict is detected.
5. The apparatus of claim 1 , wherein the lock-protected section of the second instructions is a lock-protected critical section of the second instructions, the lock-protected critical section including a loop.
6. The apparatus of claim 1 , wherein the processor circuitry is to execute the transactional process using multi-threading through lock elision.
7. The apparatus of claim 1 , wherein the processor circuitry is to execute the transactional process in the speculative execution to reduce lock contention.
8. The apparatus of claim 1 , wherein at least a portion of the second instructions corresponding to the instruction count of the second instructions are in a loop.
9. One or more non-transitory computer-readable media comprising code that, when executed, causes a machine to at least:
determine a target process has exceeded a processor utilization threshold, the target process including instructions;
determine an instruction count of the instructions satisfies a threshold;
identify a lock-protected section of the instructions;
replace lock/unlock instructions of the lock-protected section of the instructions with transactional lock acquire and transactional lock release instructions to form a transactional process; and
execute the transactional process in a speculative execution.
10. The one or more non-transitory computer-readable media of claim 9 , wherein the code is to cause the machine to execute the transactional process using lock elision.
11. The one or more non-transitory computer-readable media of claim 9 , wherein the code is to cause the machine to roll back the transactional process if a conflict is detected.
12. The one or more non-transitory computer-readable media of claim 9 , wherein the lock-protected section of the instructions is a lock-protected critical section of the instructions, the lock-protected critical section including a loop.
13. The one or more non-transitory computer-readable media of claim 9 , wherein the code is to cause the machine to execute the transactional process in the speculative execution to reduce lock contention.
14. The one or more non-transitory computer-readable media of claim 9 , wherein the instructions in the target process are in a loop.
15. One or more non-transitory computer-readable media comprising first instructions that, when executed, cause a machine to at least:
determine in response to a target process has exceeded a processor utilization threshold;
determine a loop in the target process has less than a predefined number of second instructions;
identify a lock-protected section of original code in the loop;
respectively replace lock and unlock instructions of the lock-protected section of the original code with transactional start and transactional commit instructions to form transactional code; and
execute the transactional code in a speculative execution.
16. The one or more non-transitory computer-readable media of claim 15 , wherein the first instructions are to cause the machine to detect a conflict, roll back the transactional code, and execute the original code.
17. The one or more non-transitory computer-readable media of claim 15 , wherein the lock-protected section of the original code is a lock-protected critical section.
18. The one or more non-transitory computer-readable media of claim 15 , wherein the first instructions are to cause the machine to execute the transactional code using multi-threading through lock elision.
19. The one or more non-transitory computer-readable media of claim 15 , wherein the first instructions are to cause the machine to execute the transactional code in the speculative execution to reduce lock contention.