Semiconductor device having different voltage regions

1. A semiconductor device, comprising:

a substrate having a first region and a second region;

a first gate structure disposed on the substrate within the first region;

a first source and drain (S/D) region, disposed in the substrate within the first region and beside the first gate structure, wherein the first S/D region has a first silicide layer disposed thereon;

a first S/D contact connected to the first S/D region and landing on the first silicide layer;

a first isolation structure, disposed laterally aside and in contact with the first S/D region within the first region;

a second gate structure disposed on the substrate within the second region;

a second S/D region, disposed in the substrate within the second region and beside the second gate structure, wherein the second S/D region has a second silicide layer disposed thereon;

a second S/D contact connected to the second S/D region and landing on the second silicide layer; and

a second isolation structure, disposed laterally aside and in contact with the second S/D region within the second region, wherein a top surface of the second isolation structure in the second region is lower than a top surface of the first isolation structure in the first region,

wherein a contact area between the second silicide layer of the second S/D region and the second S/D contact is larger than a contact area between the first silicide layer of the first S/D region and the first S/D contact.

2. The semiconductor device of claim 1 , wherein a height of the second S/D contact is larger than a height of the first S/D contact, and bottom surfaces of the first S/D contact and the second S/D contact are in physical contact with top surfaces of the first silicide layer and the second silicide layer, respectively.

3. The semiconductor device of claim 1 , wherein a bottom surface of the second S/D contact is lower than a bottom surface of the first S/D contact, and a top surface of the second S/D contact is substantially coplanar with a top surface of the first S/D contact.

4. The semiconductor device of claim 1 , wherein the second S/D contact has a width larger than a width of the first S/D contact.

5. The semiconductor device of claim 1 , wherein the top surface of the first isolation structure is higher than a top surface of the first silicide layer, while the top surface of the second isolation structure is level with a top surface of the second silicide layer.

6. The semiconductor device of claim 1 , wherein a top surface of the substrate in the second region is lower than a top surface of the substrate in the first region.

7. The semiconductor device of claim 1 , wherein a bottom surface of the first isolation structure is level with a bottom surface of the second isolation structure.

8. The semiconductor device of claim 1 , further comprising:

a first gate contact, connected to a first gate electrode of the first gate structure; and

a second gate contact, connected to a second gate electrode of the second gate structure,

wherein a bottom width of the first gate contact is substantially equal to a bottom width of the second gate contact.

9. A semiconductor device, comprising:

a substrate having a first region and a recessed second region;

a low voltage transistor device disposed in the first region, comprising:

a first gate structure disposed on the substrate;

a first source/drain (S/D) region disposed in the substrate and beside the first gate structure, wherein the first S/D region has a first silicide layer disposed thereon;

a first S/D contact connected to the first S/D region and landing on the first silicide layer; and

a first isolation structure, disposed laterally aside and in contact with the first S/D region within the first region; and

a high voltage transistor device disposed in the recessed second region, comprising:

a second gate structure disposed on the substrate;

a second S/D region disposed in the substrate and beside the second gate structure, wherein the second S/D region has a second silicide layer disposed thereon;

a second S/D contact connected to the second S/D region and landing on the second silicide layer; and

a second isolation structure, disposed laterally aside and in contact with the second S/D region within the second region, wherein a top surface of the second isolation structure in the second region is lower than a top surface of the first isolation structure in the first region,

wherein a source/drain contact resistance between the second silicide layer of the second S/D region and the second S/D contact of the high voltage transistor device is lower than a source/drain contact resistance between the first silicide layer of the first S/D region and the first S/D contact of the low voltage transistor device.

10. The semiconductor device of claim 9 , wherein a dimension of the second S/D contact is larger than a dimension of the first S/D contact.

11. The semiconductor device of claim 10 , further comprising:

a first gate contact connected to a first gate electrode of the first gate structure; and

a second gate contact connected to a second gate electrode of the second gate structure,

wherein a dimension of the first gate contact is substantially equal to a dimension of the second gate contact.

12. The semiconductor device of claim 9 , wherein

the first gate structure comprises: an interfacial layer, a first high-k dielectric layer on the interfacial layer and a first gate electrode on the first high-k dielectric layer;

the second gate structure comprises: a gate oxide layer, a second high-k dielectric layer on the gate oxide layer and a second gate electrode on the second high-k dielectric layer,

wherein the gate oxide layer is thick than the interfacial layer.

13. The semiconductor device of claim 9 , wherein a top surface of the first gate structure is substantially coplanar with a top surface of the second gate structure.