Synchronization in a quantum controller with modular and dynamic pulse generation and routing
View Patent ↗A quantum controller comprises a first quantum control pulse generation circuit and a second quantum control pulse generation circuit. The first quantum control pulse generation circuit and a second quantum control pulse generation circuit are operable to operate asynchronously during some time intervals of a quantum algorithm and synchronously during other time intervals of the quantum algorithm.
1. A system comprising:
a first pulse generation circuit, a second pulse generation circuit, and synchronization management circuitry, wherein:
the first pulse generation circuit and second pulse generation circuit are configured to sometimes generate pulses asynchronously with respect to each other and sometimes generate pulses synchronously with respect to each other; and
the first pulse generation circuit and the second pulse generation circuit are each configured to determine when to generate pulses synchronously based on the synchronization management circuitry.
2. The system of claim 1 , wherein the first pulse generation circuit and the second pulse generation circuit are each configured to determine when to generate pulses synchronously based a state of a synchronization register of the synchronization management circuitry.
3. The system of claim 1 , wherein each of the first pulse generation circuit and the second pulse generation circuit is operable to, when ready to begin synchronous operation:
trigger a change of state of the synchronization management circuitry;
read a state of the synchronization management circuitry; and
wait to begin synchronous operation until the state of the synchronization management circuitry indicates both the first pulse generation circuit and the second pulse generation circuit are ready to begin synchronous operation.
4. The system of claim 3 , wherein:
the synchronization management circuitry comprises a grid-step register; and
each of the first pulse generation circuit and the second pulse generation circuit is operable to, when the state of the synchronization management circuitry indicates that the first pulse generation circuit and the second pulse generation circuit are not both ready to begin synchronous operation, wait for a number of clock cycles determined based on a value stored in the grid-step register.
5. The system of claim 4 , wherein the synchronization management circuitry is operable to set the value stored in the grid-step register based on an uncertainty in how long it takes signals to propagate between the synchronization management circuitry and the first pulse generation circuit and/or between the synchronization management circuitry and the second pulse generation circuit.
6. The system of claim 3 , wherein each of the first pulse generation circuit and the second pulse generation circuit is operable to, when ready to begin synchronous operation, wait for a next on-grid clock cycle before the trigger of the change of state of the synchronization management circuitry.
7. The system of claim 6 , wherein on-grid clock cycles occur 1 out of every N clock cycles.
8. The system of claim 7 , wherein the synchronization management circuitry comprises an on-grid register that is in a first state for 1 out of every N clock cycles and is not in the first state for N-1 of every N clock cycles, wherein:
N is an integer; and
the next on-grid clock cycle is a next clock cycle in which the on-grid register is in the first state.
9. The system of claim 8 , wherein a value of N is determined based on a value stored in a grid-step register of the synchronization management circuitry.
10. The system of claim 1 , wherein the synchronization management circuitry comprises a wait time register.
11. The system of claim 10 , wherein the synchronization management circuitry is operable to set a value stored in the wait time register based on how long it takes signals to propagate between the synchronization management circuitry and the first pulse generation circuit and/or between the synchronization management circuitry and the second pulse generation circuit.
12. The system of claim 1 , wherein the first pulse generation circuit is operable to:
in response to detection of a particular value in a synchronization field of an instruction, trigger a change of state of the synchronization management circuitry;
after the trigger of the change of state, read the state of the synchronization management circuitry to determine whether the second pulse generation circuit is ready to begin synchronized pulse generation;
if the read state of the synchronization management circuitry indicates that the second pulse generation circuit is ready to begin synchronized pulse generation, begin synchronized pulse generation; and
if the read state of the synchronization management circuitry indicates that the second pulse generation circuit is not ready to begin synchronized pulse generation, wait to begin synchronized pulse generation at a later time.
13. The system of claim 12 , comprising a grid-step register, wherein if the read state of the synchronization management circuitry indicates that the second pulse generation circuit is not ready to begin synchronous operation with the first pulse generation circuit, the wait is for a number of clock cycles determined based on a grid-step register.
14. The system of claim 13 , wherein a value stored in the grid-step register is based on an uncertainty in how long it takes signals to propagate between the synchronization management circuitry and the second pulse generation circuit and/or between the synchronization management circuitry and the first pulse generation circuit.
15. The system of claim 12 , wherein the first pulse generation circuit is operable to, in response to detection of a particular value in the synchronization field, wait for a next on-grid clock cycle before the trigger of the change of state of the synchronization management circuitry.
16. The system of claim 15 , comprising an on-grid register that is in a first state for 1 out of every N clock cycles and is not in the first state for N-1 of every N clock cycles, where:
N is an integer; and
the next on-grid clock cycle is a next clock cycle in which the on-grid register is in the first state.
17. The system of claim 16 , wherein a value of N is determined based on a value stored in a grid-step register.
18. The system of claim 12 , comprising one or more third pulse generation circuits.
19. The system of claim 18 , wherein:
the instruction comprises a field containing a bitmap;
each bit of the bitmap corresponds to a respective one of the first pulse generation circuit, the second pulse generation circuit, and the one or more third pulse generation circuits; and
the bitmap indicates which of the first pulse generation circuit, the second pulse generation circuit, and the one or more third pulse generation circuits are to operate synchronously.