Apparatus and methods to provide power management for memory devices
An apparatus, such as a nonvolatile solid-state memory device, may, in some implementations, include access line bias circuitry to set a bias level associated with a deselected access line(s) of a memory core in response to mode information. In one approach, access line bias circuitry may use linear down regulation to change a voltage level on deselected access lines of a memory core. A memory access device, such as a host processor, may be provided that is capable of dynamically setting a mode of operation of a memory core of a memory device in order to manage power consumption of the memory. Other apparatuses are also provided.
1. A method, comprising:
determining whether a predicted quantity of write operations performed by a memory device satisfies a threshold;
operating the memory device in a low voltage mode based at least in part on the predicted quantity of write operations failing to satisfy the threshold, the memory device configured to operate in the low voltage mode and a high voltage mode different than the low voltage mode;
determining a bias level of a word line of the memory device based at least in part on the memory device operating in the low voltage mode; and
accessing a memory cell of the memory device based at least in part on the bias level.
2. The method of claim 1 , further comprising:
determining an information transfer parameter associated with the memory cell of the memory device, wherein operating in the low voltage mode is based at least in part on the information transfer parameter.
3. The method of claim 1 , wherein:
the low voltage mode is a read-only mode; and
the high voltage mode is a read/write mode.
4. The method of claim 1 , further comprising:
identifying data to be written to the memory cell of the memory device;
determining that the low voltage mode that the memory device is operating in is a read-only mode;
initiating operation of the memory device in the high voltage mode; and
writing the identified data to the memory cell while the memory device is operating in the high voltage mode.
5. The method of claim 1 , further comprising:
determining a bias level of a deselected word line of the memory device based at least in part on operating the memory device in the low voltage mode, wherein accessing the memory cell is based at least in part on the bias level of the deselected word line.
6. A method, comprising:
operating a memory device in a low voltage mode, the memory device configured to operate in the low voltage mode and a high voltage mode different than the low voltage mode;
determining a bias level of a word line of the memory device based at least in part on the memory device operating in the low voltage mode;
accessing a memory cell of the memory device based at least in part on the bias level; and
initiating operation of the memory device in the high voltage mode based at least in part on an amount of power consumed by the memory device, an amount of latency in one or more access operations, a number of memory cells in the memory device, or a combination thereof.
7. A method, comprising:
operating a memory device in a low voltage mode that is a low-power mode,
the memory device configured to operate in the low voltage mode and a high voltage mode that is a low-latency mode different than the low voltage mode;
determining a bias level of a word line of the memory device based at least in part on the memory device operating in the low voltage mode; and
accessing a memory cell of the memory device based at least in part on the bias level.
8. A method, comprising:
operating a memory device in a low voltage mode, the memory device configured to operate in the low voltage mode and a high voltage mode different than the low voltage mode;
determining a bias level of a word line of the memory device based at least in part on the memory device operating in the low voltage mode;
enabling an overlay window based at least in part on determining the bias level, wherein the overlay window is configured to control the bias level of the word line associated with a memory cell; and
accessing the memory cell of the memory device based at least in part on the bias level.
9. The method of claim 8 , further comprising:
writing information to a register of a command interface based at least in part on the overlay window, wherein enabling the overlay window is based at least in part on writing the information to the register.
10. A method, comprising:
operating a memory device in a low voltage mode, the memory device configured to operate in the low voltage mode and a high voltage mode different than the low voltage mode;
determining a bias level of a word line of the memory device based at least in part on the memory device operating in the low voltage mode;
controlling the bias level of the word line using a linear down regulator based at least in part on determining the bias level; and
accessing a memory cell of the memory device based at least in part on the bias level.
11. A method, comprising:
operating, by a memory device, in a low voltage mode using a first bias level of a word line of the memory device;
determining that a predicted quantity of write operations of the memory device satisfies a threshold; and
initiating operation of the memory device in a high voltage mode different from the low voltage mode based at least in part on the predicted quantity of write operations satisfying the threshold.
12. The method of claim 11 , further comprising:
determining a second bias level of the word line of the memory device based at least in part on operating in the high voltage mode, the second bias level being different than the first bias level.
13. The method of claim 12 , further comprising:
accessing a memory cell of the memory device based at least in part on the second bias level associated with the high voltage mode.
14. The method of claim 11 , wherein:
the low voltage mode is a low-power mode; and
the high voltage mode is a low-latency mode.
15. A method, comprising:
determining whether a predicted quantity of write operations performed by a memory device satisfies a threshold;
operating the memory device in a low voltage mode based at least in part on the predicted quantity of write operations failing to satisfy the threshold;
determining a first bias level of a word line of the memory device based at least in part on operating in the low voltage mode, the first bias level being less than a second bias level associated with a high voltage mode of the memory device; and
determining a logic state stored on a memory cell of the memory device using the first bias level.
16. The method of claim 15 , further comprising:
applying the first bias level to the word line during a read operation, wherein determining the logic state is based at least in part on applying the first bias level.
17. The method of claim 15 , further comprising:
enabling an overlay window based at least in part on operating in the low voltage mode, wherein the overlay window is configured to control a bias level of the word line associated with the memory cell during an access operation.
18. The method of claim 15 , further comprising:
activating a linear down regulator based at least in part on operating in the low voltage mode, wherein the linear down regulator is configured to generate the first bias level by reducing a voltage level associated with the second bias level.