Organic light emitting diode display
A diode display includes a substrate having a first island and a second island spaced apart from each other, a first pixel disposed on the first island, and a second pixel disposed on the second island. The first pixel includes a first base layer, a first transistor on the first base layer, a first light emitting element electrically connected to the first transistor, and a first encapsulation layer covering the first light emitting element. The second pixel includes a second base layer, a second transistor on the second base layer, a second light emitting element connected to the second transistor, and a second encapsulation layer covering the second light emitting element.
1. A diode display, comprising:
a substrate having a first island and a second island spaced apart from each other;
a first pixel disposed on the first island; and
a second pixel disposed on the second island,
wherein the first pixel includes a first base layer, a first transistor on the first base layer, a first light emitting element electrically connected to the first transistor, and a first encapsulation layer covering the first light emitting element, and
wherein the second pixel includes a second base layer, a second transistor on the second base layer, a second light emitting element connected to the second transistor, and a second encapsulation layer covering the second light emitting element.
2. The display of claim 1 , further comprising:
a connection area in which a bridge connecting the first pixel and the second pixel is disposed,
wherein the first encapsulation layer and the second encapsulation layer are connected to each other in the connection area.
3. The display of claim 2 , wherein the connection area has a curved shape.
4. The display of claim 2 , wherein the bridge has a curved shape.
5. The display of claim 1 , wherein the first encapsulation layer is in contact with an upper surface of the first base layer, and the second encapsulation layer is in contact with an upper surface of the second base layer.
6. The display of claim 1 , wherein:
the first pixel further includes a first buffer layer between the first base layer and the first transistor,
the second pixel further includes a second buffer layer between the second base layer and the second transistor,
the first encapsulation layer is in contact with a side surface of the first buffer layer, and
the second encapsulation layer is in contact with a side surface of the second buffer layer.
7. The display of claim 6 , wherein the first buffer layer and the second buffer layer are separated from each other.
8. The display of claim 6 , wherein:
the first pixel further includes a first insulating layer between the first buffer layer and the first transistor,
the second pixel further includes a second insulating layer between the second buffer layer and the second transistor,
the first encapsulation layer is in contact with a side surface of the first insulating layer, and
the second encapsulation layer is in contact with a side surface of the second insulating layer.
9. The display of claim 8 , wherein the first insulating layer and the second insulating layer are separated from each other.
10. The display of claim 1 , wherein each of the first base layer and the second base layer includes a plurality of pixel forming plates on which at least one subpixel is disposed.
11. A diode display, comprising:
a substrate;
a first base layer and a second base layer disposed on the substrate and spaced apart from each other;
a first transistor and a second transistor disposed on the first base layer and the second base layer, respectively;
a first light emitting element and a second light emitting element electrically connected to the first transistor and the second transistor, respectively; and
a first encapsulation layer and a second encapsulation layer covering the first light emitting element and second light emitting element, respectively.
12. The display of claim 11 , further comprising:
a connection area in which the first encapsulation layer and the second encapsulation layer are connected to each other.
13. The display of claim 12 , wherein the connection area has a curved shape.
14. The display of claim 11 , wherein the substrate includes a first island and a second island spaced from each other, and wherein the first base layer and the second base layer disposed on the first island and the second island, respectively.
15. The display of claim 11 , wherein the first encapsulation layer is in contact with an upper surface of the first base layer, and the second encapsulation layer is in contact with an upper surface of the second base layer.
16. The display of claim 11 , further comprising:
a first buffer layer between the first base layer and the first transistor; and
a second buffer layer between the second base layer and the second transistor,
wherein the first encapsulation layer is in contact with a side surface of the first buffer layer, and the second encapsulation layer is in contact with a side surface of the second buffer layer.
17. The display of claim 16 , wherein the first buffer layer and the second buffer layer are separated from each other.
18. The display of claim 16 , further comprising:
a first insulating layer between the first buffer layer and the first transistor; and
a second insulating layer between the second buffer layer and the second transistor,
wherein the first encapsulation layer is in contact with a side surface of the first insulating layer, and the second encapsulation layer is in contact with a side surface of the second insulating layer.
19. The display of claim 18 , wherein the first insulating layer and the second insulating layer are separated from each other.
20. The display of claim 11 , wherein each of the first base layer and the second base layer includes a plurality of pixel forming plates on which at least one subpixel is disposed.