Systems and methods for reduction of in-phase and quadrature-phase (IQ) clock skew

1. A clock system comprising:

an in-phase clock input and an in-phase clock output;

a quadrature clock input and a quadrature clock output;

a control loop configured to receive the in-phase clock output and the quadrature clock output, the control loop including a Boolean logic gate coupled to an operational amplifier (op-amp) through a low-pass filter; and

an analog delay element coupled between the quadrature clock input and the quadrature clock output, the analog delay element comprising a plurality of capacitors.

2. The clock system of claim 1 , wherein the control loop is configured to generate a first signal having a DC signal level corresponding to a skew between the in-phase clock output and the quadrature clock output.

3. The clock system of claim 1 , wherein the analog delay element comprises a first capacitor and a second capacitor arranged between a first set of inverters and a second set of inverters, the analog delay element coupled to the quadrature clock input.

4. The clock system of claim 1 , wherein the Boolean logic gate comprises:

a NAND gate configured to receive a reduced quadrature clock signal from the quadrature clock output and configured to receive a reduced in-phase clock signal from the in-phase clock output.

5. The clock system of claim 1 , wherein the Boolean logic gate comprises:

a NAND gate configured to receive a divided quadrature clock signal from the quadrature clock output and configured to receive a divided in-phase clock signal from the in-phase clock output.

6. The clock system of claim 1 , wherein the Boolean logic gate is configured to receive a reduced quadrature clock signal from the quadrature clock output and configured to receive a reduced in-phase clock signal from the in-phase clock output, the Boolean logic gate configured to output a signal having a duty cycle corresponding to a skew between the in-phase clock output and the quadrature clock output; and

wherein the low-pass filter comprises a resistive-capacitive (RC) filter.

7. The clock system of claim 1 , wherein the control loop comprises:

an operational amplifier (op-amp) configured to output a first signal corresponding to a difference between an output of the low-pass filter and a reference voltage signal; and

a single-to-differential voltage converter at an output of the op-amp and configured to receive the first signal and to output a differential control signal to the analog delay element.

8. The clock system of claim 1 , wherein the control loop comprises:

a comparing circuit configured to output a first signal corresponding to a difference between an output of the low-pass filter and a reference voltage signal; and

a plurality of current mirrors at an output of the comparing circuit and configured to receive the first signal and to output a differential control signal to the analog delay element.

9. The clock system of claim 1 , wherein the clock system is implemented in a serializer-deserializer (SERDES) communication link.

10. The clock system of claim 9 , including a system on chip (SoC), and wherein the SERDES communication link couples a first die in the SoC to a second die in the SoC.

11. The clock system of claim 1 , wherein the analog delay element is configured to adjust a delay of the quadrature clock output in response to a DC signal level within the control loop.

12. The clock system of claim 1 , wherein the control loop is configured to generate a first signal having a DC signal level corresponding to a skew between the in-phase clock output and the quadrature clock output, and wherein the skew represents deviation from a ninety-degree phase shift between the in-phase clock output and the quadrature clock output.

13. The clock system of claim 1 , wherein the analog delay element is configured to adjust the delay of the quadrature clock output to maintain a ninety-degree phase shift between the in-phase clock output and the quadrature clock output.

14. A method comprising:

receiving an in-phase clock signal and a quadrature clock signal at a logic gate;

generating a first signal having a DC signal level corresponding to a skew between the in-phase clock signal and the quadrature clock signal; and

controlling an analog delay element to adjust a delay of the quadrature clock signal in response to the DC signal level.

15. The method of claim 14 , wherein controlling the analog delay element comprises:

maintaining a 90-degree phase difference between the in-phase clock signal and the quadrature clock signal.

16. The method of claim 14 , wherein controlling the analog delay element comprises:

increasing or decreasing a capacitance of the analog delay element based on the DC signal level.

17. The method of claim 14 , wherein controlling the analog delay element comprises:

increasing a capacitance of the analog delay element in response to the skew indicating that the quadrature clock signal is less than 90 degrees behind the in-phase clock signal.

18. The method of claim 14 , wherein controlling the analog delay element comprises:

decreasing a capacitance of the analog delay element in response to the skew indicating that the quadrature clock signal is more than 90 degrees behind the in-phase clock signal.

19. A circuit device comprising:

means for adjusting a delay of a first clock signal relative to a second clock signal, the adjusting means placed along a clock path for the first clock signal, the adjusting means having a variable capacitance that adjusts a delay of the second clock signal;

means for comparing a phase difference between the first clock signal and the second clock signal and for generating an output signal with a signal level corresponding to the phase difference; and

means for receiving the output signal from the comparing means and for generating a control signal, in response to the output signal, to adjust the variable capacitance.

20. The circuit device of claim 19 , wherein the first clock signal comprises a quadrature clock signal, and wherein the second clock signal comprises an in-phase clock signal.

21. The circuit device of claim 19 , wherein the comparing means generates an output signal indicative of a skew of the first clock signal relative to the second clock signal, wherein the skew represents a deviation from a 90° phase difference.

22. The circuit device of claim 19 , wherein the variable capacitance comprises a negative-channel metal-oxide semiconductor (NMOS) capacitor.

23. The circuit device of claim 19 , wherein the comparing means comprises:

a Boolean logic gate receiving a reduced first clock signal and a reduced second clock signal;

a low-pass filter receiving an output from the Boolean logic gate and providing a DC signal level; and

an amplifier receiving the DC signal level and a reference voltage and outputting the signal level corresponding to the phase difference.

24. The circuit device of claim 19 , wherein the circuit device is implemented in a serializer-deserializer (SERDES) communication link.