IP Library Granted Patent US 11,527,408
Granted Patent B2
US 11,527,408 · App. 16/867,095 · Granted Dec 13, 2022

Multiple spacer patterning schemes

Inventors: Tzu-shun Yang (Milpitas, CA); Rui Cheng (Santa Clara, CA); Karthik Janakiraman (San Jose, CA); Zubin Huang (Santa Clara, CA); Diwakar Kedlaya (Santa Clara, CA); Meenakshi Gupta (San Jose, CA); Srinivas Guggilla (San Jose, CA); Yung-chen Lin (Gardena, CA); Hidetaka Oshio (Tokyo, JP); Chao Li (Santa Clara, CA); Gene Lee (San Jose, CA)
Assignee: Applied Materials, Inc.
H01L21/0338H01L21/0337H01L21/31138H01L21/32137
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Quick Facts
Patent No.
US 11,527,408
App. No.
16/867,095
Granted
Dec 13, 2022
Kind
B2
Abstract

The present disclosure provides forming nanostructures utilizing multiple patterning process with good profile control and feature transfer integrity. In one embodiment, a method for forming features on a substrate includes forming a first mandrel layer on a material layer disposed on a substrate. A first spacer layer is conformally formed on sidewalls of the first mandrel layer, wherein the first spacer layer comprises a doped silicon material. The first mandrel layer is selectively removed while keeping the first spacer layer. A second spacer layer is conformally formed on sidewalls of the first spacer layer and selectively removing the first spacer layer while keeping the second spacer layer.

Claims (19)

1. A method for forming features on a substrate comprising:

forming a first mandrel layer on a material layer disposed on a substrate;

conformally forming a first spacer layer on sidewalls of the first mandrel layer, wherein the first spacer layer has a doped silicon material;

selectively removing the first mandrel layer in an anisotropic etch process while keeping the first spacer layer, wherein the anisotropic etch process has a second RF source power setting between about 30 percent and about 80 percent higher than a first RF source power setting and a second bias power setting between about 30 percent and about 70 percent less than a first bias power setting, and wherein the first spacer layer has vertically straight sidewalls and square corners and top surface profile after selectively removing the first mandrel layer;

conformally forming a second spacer layer on sidewalls of the first spacer layer; and

selectively removing the first spacer layer while keeping the second spacer layer; and

patterning the material layer with the second spacer layer as a mask.

2. The method of claim 1 , wherein the doped silicon material has a group III, group IV or group V doped silicon material.

3. The method of claim 2 , wherein the doped silicon material is a Boron doped silicon material.

4. The method of claim 1 wherein selectively removing the first spacer layer while keeping the second spacer layer further comprises:

depositing another spacer on sidewalls of the second spacer layer conformally such that the second spacer is used as a second mandrel; and

after depositing another spacer on the sidewalls of the second spacer layer, removing the second spacer layer to shrink down a critical dimension of a feature formed on the substrate.

5. The method of claim 1 wherein the mandrel layer is trimmed by anisotropic etching to reduce a dimension of the mandrel layer from a first dimension to a second reduced dimension.

6. The method of claim 1 wherein selectively removing the mandrel layer comprises:

introducing an oxygen containing gas and/or with a carrier gas comprising one of N 2 , He, or Ar, which is utilized to remove the mandrel layer.

7. The method of claim 1 wherein conformally forming a second spacer layer on sidewalls of the first spacer layer further comprising:

anisotropicly etching a top surface of the material of the second spacer layer while maintaining the remaining sidewalls of the second spacer layer to assist in reducing dimensions of openings between spacer structures formed by the first and second spacer layers.

8. The method of claim 1 further comprising:

forming an opening in the second spacer layer by selectively removing the first spacer layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 22, 2022
From: YANG, TZU-SHUN; CHENG, RUI; JANAKIRAMAN, KARTHIK; HUANG, ZUBIN; KEDLAYA, DIWAKAR N.; GUPTA, MEENAK; GUGGILLA, SRINIVAS; LIN, YUNG-CHEN; OSHIO, HIDETAKA; LI, CHAO; LEE, GENE
To: APPLIED MATERIALS, INC.
Reel/Frame 059336/0143 →
Continuity (3)
Continuation 16821759 · Mar 17, 2020
Provisional Application 62835290 · Apr 17, 2019
Related Publication 20200335339A1 · Oct 22, 2020