Dynamically adjustable CMOS circuit
A complementary metal-oxide semiconductor (CMOS) circuit comprises an inverter, a plurality of P-type metal-oxide semiconductor (PMOS) transistors, and a plurality of N-type metal-oxide semiconductor (NMOS) transistors. The inverter receives an input signal and drives one of the plurality of PMOS transistors or the plurality of NMOS transistors. The plurality of PMOS transistors generate a pull-up signal, change a beta ratio of the CMOS circuit, and change a first trip point of the CMOS circuit to a second trip point of the CMOS circuit based on the changed beta ratio. The plurality of NMOS transistors generate a pull-down signal, change the beta ratio, and change the second trip point of the CMOS circuit to a third trip point of the CMOS circuit based on the changed beta ratio.
1. A complementary metal-oxide semiconductor (CMOS) circuit, comprising:
a first inverter;
a plurality of P-type metal-oxide semiconductor (PMOS) transistors; and
a plurality of N-type metal-oxide semiconductor (NMOS) transistors,
wherein the first inverter is configured to:
receive an input signal; and
drive one of the plurality of PMOS transistors or the plurality of NMOS transistors, based on the received input,
wherein the plurality of PMOS transistors are configured to:
generate a pull-up signal;
change a beta ratio of the CMOS circuit from a first value to a second value,
based on the generated pull-up signal; and
change a first trip point of the CMOS circuit to a second trip point of the CMOS circuit, based on the second value of the beta ratio, and
wherein the plurality of NMOS transistors are configured to:
generate a pull-down signal;
change the beta ratio from the second value to a third value, based on the generated pull-down signal; and
change the second trip point of the CMOS circuit to a third trip point of the CMOS circuit, based on the third value of the beta ratio, wherein,
a gate terminal of each of a first PMOS transistor and a second PMOS transistor of the plurality of PMOS transistors is connected to an input terminal of the first inverter;
a gate terminal of a third PMOS transistor of the plurality of PMOS transistors is connected to an output terminal of the first inverter; and
a gate terminal of each of a first NMOS transistor and a second NMOS transistor of the plurality of PMOS transistors is connected to the input terminal of the first inverter; and
a second inverter configured to output a feedback signal to the input terminal of the first inverter.
2. The CMOS circuit of claim 1 , wherein a gate terminal of a third NMOS transistor of the plurality of NMOS transistors is connected to the output terminal of the first inverter.
3. The CMOS circuit of claim 1 , wherein each of the first trip point, the second trip point, and the third trip point of the CMOS circuit is associated with a corresponding threshold voltage level.
4. The CMOS circuit of claim 1 , wherein the first inverter is a Schmitt trigger.
5. The CMOS circuit of claim 1 , wherein a drain terminal of the first PMOS transistor is connected to a first source voltage and a source terminal of the third PMOS transistor is connected to a second source voltage.
6. The CMOS circuit of claim 1 , wherein a source terminal of the second PMOS transistor is connected to a drain terminal of the third PMOS transistor.
7. The CMOS circuit of claim 1 , wherein a source terminal of the first NMOS transistor is connected to ground and wherein a source terminal of the second NMOS transistor is connected to the ground.
8. The CMOS circuit of claim 1 , wherein a drain terminal of the second NMOS transistor is connected to a source terminal of the third NMOS transistor.
9. The CMOS circuit of claim 1 , wherein the first PMOS transistor is a pull-up PMOS transistor, and wherein the first NMOS transistor is a pull-down NMOS transistor.
10. The CMOS circuit of claim 1 , wherein the second PMOS transistor is configured to execute a skew-rise operation.
11. The CMOS circuit of claim 1 , wherein the second NMOS transistor is configured to execute a skew-fall operation.
12. A complementary metal-oxide semiconductor (CMOS) circuit, comprising:
a first inverter;
a plurality of P-type metal-oxide semiconductor (PMOS) transistors; and
a plurality of N-type metal-oxide semiconductor (NMOS) transistors,
wherein the first inverter is configured to:
receive an input signal; and
drive one of the plurality of PMOS transistors or the plurality of NMOS transistors, based on the received input,
wherein the plurality of PMOS transistors are configured to:
generate a pull-up signal;
change a beta ratio of the CMOS circuit from a first value to a second value,
based on the generated pull-up signal; and
change a first trip point of the CMOS circuit to a second trip point of the CMOS circuit, based on the second value of the beta ratio, and
wherein the plurality of NMOS transistors are configured to:
generate a pull-down signal;
change the beta ratio from the second value to a third value, based on the generated pull-down signal; and
change the second trip point of the CMOS circuit to a third trip point of the CMOS circuit, based on the third value of the beta ratio, wherein,
a gate terminal of each of a first PMOS transistor and a second PMOS transistor of the plurality of PMOS transistors is connected to an input terminal of the first inverter;
a gate terminal of a third PMOS transistor of the plurality of PMOS transistors is connected to an output terminal of the first inverter; and
a gate terminal of each of a first NMOS transistor and a second NMOS transistor of the plurality of PMOS transistors is connected to the input terminal of the first inverter; and
a second inverter configured to output a feedback signal to the input terminal of the first inverter, wherein the second inverter is connected to a drain terminal of each of the first PMOS transistor, the second PMOS transistor, the first NMOS transistor, and the second NMOS transistor.
13. The CMOS circuit of claim 12 , wherein a gate terminal of a third NMOS transistor of the plurality of NMOS transistors is connected to the output terminal of the first inverter.
14. The CMOS circuit of claim 12 , wherein each of the first trip point, the second trip point, and the third trip point of the CMOS circuit is associated with a corresponding threshold voltage level.
15. The CMOS circuit of claim 12 , wherein the first inverter is a Schmitt trigger.
16. The CMOS circuit of claim 12 , wherein a drain terminal of the first PMOS transistor is connected to a first source voltage and a source terminal of the third PMOS transistor is connected to a second source voltage.
17. The CMOS circuit of claim 12 , wherein a source terminal of the second PMOS transistor is connected to a drain terminal of the third PMOS transistor.
18. The CMOS circuit of claim 12 , wherein a source terminal of the first NMOS transistor is connected to ground and wherein a source terminal of the second NMOS transistor is connected to the ground.
19. The CMOS circuit of claim 12 , wherein a drain terminal of the second NMOS transistor is connected to a source terminal of the third NMOS transistor.
20. The CMOS circuit of claim 12 , wherein the first PMOS transistor is a pull-up PMOS transistor, and wherein the first NMOS transistor is a pull-down NMOS transistor.
21. The CMOS circuit of claim 12 , wherein the second PMOS transistor is configured to execute a skew-rise operation.
22. The CMOS circuit of claim 12 , wherein the second NMOS transistor is configured to execute a skew-fall operation.