Pixel and related organic light emitting diode display device
A pixel of a display device includes a capacitor; a light emitting diode; and first, second, third, and fourth transistors. The display device has a normal frequency mode and a low frequency mode. Two electrodes of the capacitor are respectively connected to a first voltage source and a gate node. A gate electrode of the first transistor is connected to the gate node. In a hold period in the low frequency mode, both the second and third transistors receive a scan signal, the third transistor diode-connects the first transistor, the fourth transistor receives an initialization signal and transfers an initialization voltage to the gate node, the scan signal is at a first off voltage level, and the initialization signal is at a second off voltage level unequal to the first off voltage level. The cathode of the light emitting diode is connected to a second voltage source.
1. A pixel of a display device, the display device having a first mode and a second mode, a driving frequency of the second mode being lower than a driving frequency of the first mode, the pixel comprising:
a capacitor, wherein a first electrode of the capacitor receives a first power supply voltage, and wherein a second electrode of the capacitor is electrically connected to a gate node;
a first transistor, wherein a gate electrode of the first transistor is electrically connected to the gate node;
a second transistor, wherein a drain electrode of the second transistor is electrically connected to a source electrode of the first transistor, and wherein a gate electrode of the second transistor receives a first instance of a scan signal in a hold period in the second mode;
a third transistor diode-connecting the first transistor in response to a second instance of the scan signal in the hold period in the second mode;
a fourth transistor transferring an initialization voltage to the gate node in response to a first instance of an initialization signal in the hold period in the second mode; and
an organic light emitting diode including an anode and a cathode, wherein the cathode receives a second power supply voltage different from the first power supply voltage, wherein in the hold period in the second mode, the scan signal and the initialization signal have different off voltage levels.
2. The pixel of claim 1 , wherein the hold period includes one of consecutive frame periods in the second mode.
3. The pixel of claim 1 , wherein in a frame period in the first mode, the scan signal changes from an on voltage level to a first off voltage level at a first time, and the initialization signal changes from the on level to the first off voltage level at a second time different from the first time, and
wherein in the hold period in the second mode, the initialization signal is increased from the first off voltage level to a second off voltage level higher than the first off voltage level.
4. The pixel of claim 3 , wherein in the hold period in the second mode, a leakage current of the fourth transistor is increased based on a difference between the second off voltage level and the first off voltage level.
5. The pixel of claim 3 , wherein a difference between the second off voltage level and the first off voltage level depends on the driving frequency of the second mode.
6. The pixel of claim 1 , wherein in a frame period in the first mode, the scan signal changes from an on voltage level to a first off voltage level at a first time, and the initialization signal changes from the on level to the first off voltage level at a second time different from the first time, and
wherein in the hold period in the second mode, the scan signal is increased from the first off voltage level to a second off voltage level higher than the first off voltage level.
7. The pixel of claim 6 , wherein in the hold period in the second mode, a leakage current of the third transistor from the gate node to a drain electrode of the first transistor is increased based on a difference between the first off voltage level and the second off voltage level.
8. The pixel of claim 1 , wherein in a frame period in the first mode, the scan signal changes from an on voltage level to a first off voltage level at a first time, and the initialization signal changes from the on level to the first off voltage level at a second time different from the first time, and
wherein in the hold period in the second mode, the initialization signal is decreased from the first off voltage level to a second off voltage level lower than the first off voltage level.
9. The pixel of claim 8 , wherein in the hold period in the second mode, a leakage current of the fourth transistor is decreased based on a difference between the second off voltage level and the first off voltage level.
10. The pixel of claim 1 , wherein in a frame period in the first mode, the scan signal changes from an on voltage level to a first off voltage level at a first time, and the initialization signal changes from the on level to the first off voltage level at a second time different from the first time, and
wherein in the hold period in the second mode, the scan signal is decreased from the first off voltage level to a second off voltage level lower than the first off voltage level.
11. The pixel of claim 10 wherein in the hold period in the second mode, a leakage current of the third transistor is decreased based on a difference between the first off voltage level and the second off voltage level.
12. The pixel of claim 1 , wherein the third transistor includes a first sub-transistor and a second sub-transistor that are electrically connected in series between the gate node and a drain of the first transistor, and
wherein the fourth transistor includes a third sub-transistor and a fourth sub-transistor that are electrically connected in series between the gate node and a source of the initialization voltage.
13. The pixel of claim 1 , further comprising:
a fifth transistor, wherein a gate electrode of the fifth transistor is electrically connected to an emission signal source, wherein a source electrode of the fifth transistor receives the first power supply voltage, and wherein a drain electrode of the fifth transistor is electrically connected to the source electrode of the first transistor;
a sixth transistor, wherein a gate electrode of the sixth transistor is electrically connected to the emission signal source, wherein a source electrode is electrically connected to a drain electrode of the first transistor, and wherein a drain of the sixth transistor is electrically connected to the anode of the organic light emitting diode; and
a seventh transistor, wherein a gate electrode of the seventh transistor receives a second instance of the initialization signal, wherein a source electrode of the seventh transistor is electrically connected to the anode of the organic light emitting diode, and wherein a drain electrode of the seventh transistor is electrically connected to a source of the initialization voltage.
14. A pixel of a display device, the display device having a first mode and a second mode, a driving frequency of the second mode being lower than a driving frequency of the first mode, the pixel comprising:
a capacitor, wherein a first electrode of the capacitor receives a first power supply voltage, and wherein a second electrode of the capacitor is electrically connected to a gate node;
a first transistor, wherein a gate electrode of the first transistor is electrically connected to the gate node;
a second transistor, wherein a drain electrode of the second transistor is electrically connected to a source electrode of the first transistor, and wherein a gate electrode of the second transistor receives a first instance of a scan signal in a hold period in the second mode;
a third transistor diode-connecting the first transistor in response to a second instance of the scan signal in the hold period in the second mode;
a fourth transistor transferring an initialization voltage to the gate node in response to a first instance of an initialization signal in the hold period in the second mode; and
an organic light emitting diode including an anode and a cathode, wherein the cathode receives a second power supply voltage different from the first power supply voltage,
wherein at an end of a frame period in the first mode, each of the scan signal and the initialization signal is at a first off voltage level, and
wherein in a hold period in the second mode, at least one of the scan signal and the initialization signal is at a second off voltage level unequal to the first off voltage level.
15. An organic light emitting diode (OLED) display device comprising:
a display panel including pixels;
a data driver electrically connected to the display panel and configured to provide data signals to the pixels;
a power management circuit;
a scan driver electrically connected to the power management circuit, electrically connected to the display panel, and including an initialization stage group configured to sequentially provide initialization signals to the pixels, and a scan stage group configured to sequentially provide scan signals to the pixels; and
a controller configured to control the data driver, the power management circuit, and the scan driver,
wherein in a frame period in a first mode of the OLED display device, the power management circuit provides a first gate off voltage to each of the initialization stage group and the scan stage group, and
wherein in a hold period in a second mode of the OLED display device, the power management circuit provides the first gate off voltage to a first one of the initialization stage group and the scan stage group, and provides a second gate off voltage unequal to the first gate off voltage to a second one of the initialization stage group and the scan stage group.
16. The OLED display device of claim 15 , wherein the power management circuit includes:
a switching block configured to receive a hold flag signal from the controller and configured to selectively provide the first gate off voltage or the second gate off voltage to the second one of the initialization stage group and the scan stage group in response to the hold flag signal.
17. The OLED display device of claim 16 , wherein the switching block includes:
a first switch configured to provide the first gate off voltage to the second one of the initialization stage group and the scan stage group in response to the hold flag signal; and
a second switch configured to provide the second gate off voltage to the second one of the initialization stage group and the scan stage group in response to the hold flag signal.
18. The OLED display device of claim 15 , wherein the controller includes:
a still image detector configured to receive input image data at an input frame frequency, and
wherein when the still image detector determines that the input image data represents a still image, the controller sets at least one of consecutive frame periods as the hold period in the second mode, such that the display panel operates in the second mode at a frequency lower than the input frame frequency.
19. The OLED display device of claim 15 , wherein the display panel is divided into panel regions,
wherein the controller includes:
a still image detector configured to receive input image data for the display panel at an input frame frequency and to divide the input image data into partial image data sets for the panel regions, respectively, and
wherein when the still image detector determines that an identified partial image data set of the partial image data sets represents a still image, the controller sets at least one of consecutive frame periods as the hold period in the second mode for a corresponding panel region of the panel regions that corresponds to the identified partial image data set, such that the corresponding panel region operates in the second mode at a frequency lower than the input frame frequency.
20. The OLED display device of claim 19 , wherein the second one of the initialization stage group and the scan stage group includes stage sub-groups respectively electrically connected to the panel regions, and
wherein the power management circuit includes:
switching blocks respectively electrically connected to the stage sub-groups and configured to selectively provide the first gate off voltage or the second gate off voltage to each of the stage sub-groups.