Sidewall spacer structure to increase switching performance of ferroelectric memory device

1. An integrated chip, comprising:

a pair of source/drain regions disposed in a substrate;

a gate dielectric layer disposed over the substrate and laterally between the pair of source/drain regions; and

a ferroelectric structure overlying the gate dielectric layer, wherein the ferroelectric structure comprises a ferroelectric layer and a sidewall spacer structure, wherein the sidewall spacer structure continuously laterally wraps around the ferroelectric layer, and wherein the ferroelectric layer comprises a first metal oxide and the sidewall spacer structure comprises a second metal oxide different than the first metal oxide, wherein a bottom surface of the sidewall spacer structure is disposed above a bottom surface of the ferroelectric layer.

2. The integrated chip according to claim 1 , wherein the first metal oxide is hafnium oxide and the second metal oxide is aluminum oxide.

3. The integrated chip according to claim 1 , wherein a top surface of the sidewall spacer structure is aligned with a top surface of the ferroelectric layer.

4. The integrated chip according to claim 1 , wherein the sidewall spacer structure continuously extends from a sidewall of the ferroelectric layer to contact an upper surface of the ferroelectric layer.

5. The integrated chip according to claim 1 , further comprising:

a first conductive structure disposed between the ferroelectric structure and the gate dielectric layer;

a second conductive structure overlying the ferroelectric structure; and

a gate electrode disposed between the first conductive structure and the gate dielectric layer.

6. The integrated chip according to claim 5 , wherein outer sidewalls of the sidewall spacer structure are aligned with outer sidewalls of the gate electrode.

7. The integrated chip according to claim 5 , wherein the sidewall spacer structure directly contacts a bottom surface of the second conductive structure.

8. The integrated chip according to claim 5 , wherein outer sidewalls of the sidewall spacer structure are aligned with outer sidewalls of the first conductive structure and outer sidewalls of the ferroelectric layer.

9. The integrated chip according to claim 1 , wherein outer sidewalls of the sidewall spacer structure are aligned with outer sidewalls of the gate dielectric layer.

10. An integrated chip, comprising:

a first conductive structure overlying a substrate;

a second conductive structure overlying the first conductive structure;

a ferroelectric layer arranged between the first conductive structure and the second conductive structure, wherein the ferroelectric layer underlies the second conductive structure; and

a sidewall spacer layer disposed on opposing sides of the ferroelectric layer, wherein the sidewall spacer layer continuously laterally extends around and directly contacts a perimeter of the of the ferroelectric layer, wherein an outermost sidewall of the second conductive structure is aligned with an outermost sidewall of the sidewall spacer layer.

11. The integrated chip of claim 10 , wherein the ferroelectric layer comprises a first dielectric material and the sidewall spacer layer comprises a second dielectric material different than the first dielectric material.

12. The integrated chip of claim 10 , wherein a width of the ferroelectric layer discretely decreases from a bottom surface of the ferroelectric layer in a direction towards the second conductive structure.

13. The integrated chip of claim 10 , wherein an outermost sidewall of the ferroelectric layer is aligned with the outermost sidewall of the second conductive structure and the outermost sidewall of the sidewall spacer layer.

14. The integrated chip of claim 10 , wherein a bottom surface of the ferroelectric layer directly contacts a top surface of the first conductive structure, and wherein a bottom surface of the sidewall spacer layer is vertically offset from the top surface of the first conductive structure by a non-zero distance.

15. The integrated chip of claim 10 , further comprising:

a gate dielectric layer overlying the substrate; and

a gate electrode overlying the gate dielectric layer, wherein the gate electrode directly contacts a bottom surface of the first conductive structure.

16. The integrated chip of claim 10 , wherein the sidewall spacer layer directly contacts a bottom surface of the second conductive structure in a region extending continuously from the outermost sidewall of the second conductive structure in a direction towards a center of the second conductive structure.

17. An integrated chip, comprising:

a bottom electrode overlying a substrate;

a top electrode overlying the bottom electrode; and

a ferroelectric structure disposed between the top and bottom electrodes, wherein the ferroelectric structure comprises a ferroelectric layer and a sidewall spacer structure that laterally encloses a middle region of the ferroelectric layer, wherein the ferroelectric layer has a first width and the sidewall spacer structure has a second width less than the first width, and wherein the sidewall spacer structure comprises aluminum oxide, wherein a height of the ferroelectric layer is greater than a height of the sidewall spacer structure.

18. The integrated chip of claim 17 , wherein when viewed from above the sidewall spacer structure is ring-shaped.

19. The integrated chip of claim 17 , wherein outer sidewalls of the ferroelectric layer are aligned with outer sidewalls of the bottom electrode and outer sidewalls of the ferroelectric layer.

20. The integrated chip of claim 17 , wherein the sidewall spacer structure directly contacts a sidewall and a lower surface of the ferroelectric layer.