Method and apparatus for receiving data packets
A receiver receives a data packet with a header and a payload. The payload includes at least one full service data unit, one or two service data unit fragments, or at least one full service data unit and at least one service data unit fragment, where a service data unit fragment is only located (i) at the beginning of the payload or at the end of the payload or (ii) at the beginning of the payload and at the end of the payload. The header includes a single field consisting of a first bit and a second bit, even when a number of full service data units and service data unit fragments in the payload is more than two, the single field indicating whether (i) the payload begins with a fragment of a service data unit and (ii) the payload ends with a service data unit fragment. Digital signal processing circuitry processes the header to determine processing for the payload.
1. A method for receiving a data packet having a header and a payload, comprising steps of:
receiving at a receiver the data packet, wherein:
the payload includes at least one full service data unit, one or two service data unit fragments, or at least one full service data unit and at least one service data unit fragment, where a service data unit fragment is only located (i) at the beginning of the payload or at the end of the payload or (ii) at the beginning of the payload and at the end of the payload;
the header includes a single field consisting of a first bit and a second bit, even when a number of full service data units and service data unit fragments in the payload is more than two, the single field indicating whether (i) the payload begins with a fragment of a service data unit and (ii) the payload ends with a service data unit fragment; and
processing, using digital signal processing circuitry, the header to determine processing for the payload.
2. The method according to claim 1 , wherein the first bit indicates whether the payload begins with a service data unit fragment and the second bit indicates whether the payload ends with a service data unit fragment.
3. The method according to claim 2 , wherein the payload includes at least one full service data unit, a first service data unit fragment configured at the beginning of the payload, and a second service data unit fragment configured at the end of the payload.
4. The method according to claim 1 , wherein the processing is performed by a combination of at least one digital signal processor and at least one application specific integrated circuit, field programmable gate array, or other programmable logic device.
5. An apparatus for receiving a data packet having a header and a payload, comprising:
a receiver to receive the data packet, wherein:
the payload includes at least one full service data unit, one or two service data unit fragments, or at least one full service data unit and at least one service data unit fragment, where a service data unit fragment is only located (i) at the beginning of the payload or at the end of the payload or (ii) at the beginning of the payload and at the end of the payload;
the header includes a single field consisting of a first bit and a second bit, even when a number of full service data units and service data unit fragments in the payload is more than two, the single field indicating whether (i) the payload begins with a fragment of a service data unit and (ii) the payload ends with a service data unit fragment; and
digital signal processing circuitry to process the header to determine processing for the payload.
6. The apparatus according to claim 5 , wherein the first bit indicates whether the payload begins with a service data unit fragment and the second bit indicates whether the payload ends with a service data unit fragment.
7. The apparatus according to claim 6 , wherein the payload includes at least one full service data unit, a first service data unit fragment configured at the beginning of the payload, and a second service data unit fragment configured at the end of the payload.
8. The apparatus according to claim 5 , wherein the digital signal processing circuitry comprises a digital signal processor, a application specific integrated circuit, a field programmable gate array, or other programmable logic device.
9. At least one non-transitory, computer-readable storage medium encoded with instructions which, when executed by digital signal processing circuitry, cause the digital signal processing circuitry to:
detect reception at a receiver of a data packet having a header and a payload, wherein:
the payload includes at least one full service data unit, one or two service data unit fragments, or at least one full service data unit and at least one service data unit fragment, where a service data unit fragment is only located (i) at the beginning of the payload or at the end of the payload or (ii) at the beginning of the payload and at the end of the payload;
the header includes a single field consisting of a first bit and a second bit, even when a number of full service data units and service data unit fragments in the payload is more than two, the single field indicating whether (i) the payload begins with a fragment of a service data unit and (ii) the payload ends with a service data unit fragment; and
process the header to determine processing for the payload.
10. The at least one non-transitory, computer-readable storage medium according to claim 9 , wherein the first bit indicates whether the payload begins with a service data unit fragment and the second bit indicates whether the payload ends with a service data unit fragment.
11. The at least one non-transitory, computer-readable storage medium according to claim 10 , wherein the payload includes at least one full service data unit, a first service data unit fragment configured at a beginning of the payload, and a second service data unit fragment configured at an end of the payload.
12. The at least one non-transitory, computer-readable storage medium according to claim 9 , wherein the processing is performed by a combination of at least one digital signal processor and at least one application specific integrated circuit, field programmable gate array, or other programmable logic device.