Method and apparatus for reducing light leakage at memory nodes in CMOS image sensors

1. A semiconductor device, comprising:

a light-sensing region;

a charge-storage region;

a transfer gate formed over the charge-storage region;

a light-shielding structure; and

at least one via contact;

wherein the charge-storage region is spatially configured adjacent to the light-sensing region in a lateral direction, wherein the light-shielding structure is configured over the charge-storage region in a vertical direction so as to prevent incident light leaking from the light-sensing region to the charge-storage region, wherein the light-shielding structure is configured in an interlayer dielectric (ILD) layer, wherein the light-shielding structure comprises a first surface and a second surface, wherein the first surface is coplanar with the ILD layer, and the second surface comprises a plurality of wrinkles, wherein each of the plurality of wrinkles comprises a respective lower portion that is higher than an upper portion of the transfer gate, and wherein the light-shielding structure is simultaneously formed with the at least one via contact.

2. The semiconductor device of claim 1 , wherein the light-shielding structure comprises a first thickness measured between the first surface and a highest point of the second surface, wherein the first thickness is equal to or greater than 150 nanometers.

3. The semiconductor device of claim 1 , wherein the light-shielding structure comprises tungsten (W) metal and electrically grounded through at least one grounding contact.

4. The semiconductor device of claim 1 , wherein a second thickness of the ILD layer is at least 330 nanometers.

5. The semiconductor device of claim 1 , wherein the charge-storage region comprises a charge-storage node.

6. The semiconductor device of claim 1 , wherein the light-sensing region comprises a complementary metal-oxide-semiconductor (CMOS) photodiode.

7. The semiconductor device of claim 1 , wherein the at least one via contact is configured to provide electrical contacts to the charge-storage region and is electrically isolated from the light-shielding structure, wherein the at least one via contact comprises W metal.

8. A Complementary Metal-Oxide-Semiconductor (CMOS) image sensor, comprising:

a plurality of pixels configured in a pixel array,

wherein each of the plurality of pixels comprises:

a light-sensing region;

a charge-storage region formed adjacent to the light-sensing region in a lateral direction;

a transfer gate formed over the charge-storage region;

a light-shielding structure formed over the charge-storage region in a vertical direction so as to prevent incident light leaking from the light-sensing region to the charge-storage region, wherein the light-shielding structure is configured in an interlayer dielectric (ILD) layer, wherein the light-shielding structure comprises a first surface and a second surface, wherein the first surface is coplanar with the ILD layer, and wherein the second surface comprises a plurality of wrinkles, wherein each of the plurality of wrinkles comprises a respective lower portion that is higher than an upper portion of the transfer gate; and

at least one via contact that extends through the ILD layer to contact a top surface of the transfer gate.

9. The CMOS image sensor of claim 8 , wherein each of the plurality of light-shielding structures comprises a first thickness measured between the first surface and a highest point of the second surface, wherein the first thickness is equal to or greater than 150 nanometers.

10. The CMOS image sensor of claim 8 , wherein the light-shielding structure in each of the plurality of pixels comprises tungsten (W) metal and electrically grounded through at least one grounding contact.

11. The CMOS image sensor of claim 8 , wherein a second thickness of the ILD layer is at least 330 nanometers.

12. The CMOS image sensor of claim 8 , wherein the charge-storage region comprises a charge-storage node.

13. The CMOS image sensor of claim 8 , wherein the at least one via contact is configured to provide electrical contacts to the charge-storage region and is electrically isolated from the light-shielding structure, wherein the at least one via contact comprises W metal.

14. The CMOS image sensor of claim 8 , further comprising:

a vertical shift register (VSR) coupled with the pixel array to perform at least one of the following functions, receiving a row address of the pixel array and driving control lines of the pixel array;

a horizontal shift register (HSR) coupled with the pixel array to perform reading output signals from the pixel array;

a timing generator coupled to the pixel array, the VSR and the HSR so as to generate a clock signal for synchronization purposes; and

a voltage regulator coupled to the pixel array, the VSR and the HSR so as to provide voltage control and maintain voltage levels.

15. A semiconductor device, comprising:

a light-sensing region;

a charge-storage region;

a transfer gate formed over the charge-storage region;

a light-shielding structure; and

at least one via contact;

wherein the light-shielding structure is configured in an interlayer dielectric (ILD) layer, and wherein the light-shielding structure is simultaneously formed with the at least one via contact, and wherein the light-shielding structure comprises a first surface and a second surface, the first surface being coplanar with the ILD layer, and the second surface comprises a plurality of wrinkles, wherein each of the plurality of wrinkles comprises a respective lower portion that is higher than an upper portion of the transfer gate.

16. The semiconductor device of claim 15 , wherein the charge-storage region is spatially configured adjacent to the light-sensing region in a lateral direction, wherein the light-shielding structure is configured over the charge-storage region in a vertical direction so as to prevent incident light leaking from the light-sensing region to the charge-storage region.

17. The semiconductor device of claim 15 , wherein the light-shielding structure comprises tungsten (W) metal and electrically grounded through at least one grounding contact.

18. The semiconductor device of claim 15 , wherein a first thickness of the light-shielding structure is at least 150 nanometers, and wherein a second thickness of the ILD layer is at least 330 nanometers.

19. The semiconductor device of claim 15 , wherein the charge-storage region comprises a charge-storage node.

20. The semiconductor device of claim 15 , wherein the light-sensing region comprises a complementary metal-oxide-semiconductor (CMOS) photodiode.