Systems and methods for efficient input and output to quantum processors
A quantum processor performs input and output which may be performed synchronously. The quantum processor executes a problem to generate a classical output state, which is read out at least partially by an I/O system. The I/O system also transmits a classical input state to by the I/O system, which may include the same qubit-proximate devices used for read-out. The classical input state is written to the qubits, and the quantum processor executes based on the classical input state (e.g., by performing reverse annealing to transform the classical input state to quantum state).
1. A method for synchronous input and output to a quantum processor, the quantum processor comprising a plurality of qubits coupleable to an input-output system comprising a bus, the method performed by the quantum processor and comprising:
executing a problem by the quantum processor and thereby generate a first output state based on a problem represented by the quantum processor;
reading at least a first portion of the first output state from at least a first subset of the qubits to the bus;
transmitting the first portion of the first output state along the bus to an output destination;
synchronously with transmitting the first portion of the first output state, transmitting at least a first portion of a first input state along the bus from an input source;
writing the first portion of the first input state to the first subset of the qubits; and
executing the problem by the quantum processor and thereby generate a second output state based on the first portion of the first input state.
2. The method of claim 1 wherein executing the problem based on the first portion of the first input state comprises executing the problem in reverse from the first input state to a second output state, the first input state comprising a classical state and the second output state comprising a quantum state.
3. The method of claim 2 wherein the quantum processor comprises a quantum annealing processor and executing the problem in reverse comprises reverse annealing.
4. The method of claim 3 wherein executing the problem and thereby generate a second output state comprises generating a first intermediate state by reverse annealing and generating the second output state, at least in part, by forward annealing.
5. The method of claim 1 wherein the bus comprises a plurality of shift registers and transmitting the at least a first portion of the first input state along the bus synchronously with transmitting the first portion of the first output state along the bus comprises synchronously shifting the first portion of the first input state and the first portion of the first output state along the bus.
6. The method of claim 1 wherein the input-output system comprises a plurality of latches, the plurality of qubits coupleable to the bus via the plurality of latches, and reading at least the first portion of the first output state from at least the first subset of the qubits to the bus comprises:
reading the first output state from the plurality of qubits to the plurality of latches, and
reading at least the first portion of the first output state from at least a first subset of the plurality of latches to the bus, the at least the first subset of the plurality of latches corresponding to the at least the first subset of the qubits.
7. The method of claim 6 further comprising storing at least a second portion of the first output state by the plurality of latches while transmitting at least some of the first portion of the first output state along the bus.
8. The method of claim 5 wherein synchronously shifting the first portion of the first input state and the first portion of the first output state along the bus comprises setting a first subset of the plurality of shift registers to latch and setting a second subset of the plurality of shift registers to suppress.
9. The method of claim 8 wherein setting the first subset of the plurality of shift registers to latch comprises setting a first latched shift register to latch, the first latched shift register neighboring a first holding shift register in a first direction, and setting the second subset of the plurality of shift registers to suppress comprises setting a first suppressed shift register to suppress, the first suppressed shift register neighboring the first holding shift register in a second direction opposing the first direction, the first holding shift register holding a unit of the first portion of the first input state.
10. The method of claim 9 wherein setting the first subset of the plurality of shift registers to latch comprises setting a second latched shift register to latch, the second latched shift register neighboring a second holding shift register in the first direction, and setting the second subset of the plurality of shift registers to suppress comprises setting a second suppressed shift register to suppress, the first suppressed shift register neighboring the second holding shift register in the second direction opposing the first direction, the second holding shift register holding a unit of the first portion of the first output state.
11. The method of claim 9 wherein synchronously shifting the first portion of the first input state and the first portion of the first output state along the bus comprises synchronously shifting the first portion of the first input state and the first portion of the first output in the first direction.
12. The method of claim 1 further comprising:
reading at least a first portion of the second output state from at least the first subset of the qubits to the bus;
transmitting the first portion of the second output state along the bus to the output destination;
synchronously with transmitting the first portion of the second output state, transmitting at least a first portion of a second input state along the bus from the input source;
writing the first portion of the second input state to the first subset of the qubits; and
executing the problem and thereby generating a third output state based on the first portion of the second input state.
13. The method of claim 1 further comprising discarding at least a second portion of the first output state.
14. A computing system comprising:
at least one processor in communication with a quantum processor, the quantum processor comprising a plurality of qubits coupleable to an input-output system comprising a bus;
at least one nontransitory processor-readable medium communicatively coupled to the at least one processor, the at least one nontransitory processor-readable medium storing at least one of processor-executable instructions or data which, when executed by the at least one processor, cause the at least one processor to cause the quantum processor to:
execute a problem by the quantum processor and thereby generate a first output state based on a problem represented by the quantum processor;
read at least a first portion of the first output state from at least a first subset of the qubits to the bus;
transmit the first portion of the first output state along the bus to an output destination;
synchronously with transmitting the first portion of the first output state, transmit at least a first portion of a first input state along the bus from an input source;
write the first portion of the first input state to the first subset of the qubits; and
execute the problem by the quantum processor and thereby generate a second output state based on the first portion of the first input state.
15. The computing system of claim 14 wherein the at least one processor causes the quantum processor to execute the problem in reverse from the first input state to a second output state, the first input state comprising a classical state and the second output state comprising a quantum state.
16. The computing system of claim 15 wherein the quantum processor comprises a quantum annealing processor and the at least one processor causes the quantum annealing processor to execute the problem in reverse by reverse annealing.
17. The computing system of claim 16 wherein the at least one processor causes the quantum processor to generate a first intermediate state by reverse annealing and generate the second output state, at least in part, by forward annealing.
18. The computing system of claim 14 wherein the bus comprises a plurality of shift registers and the at least one processor causes the quantum processor to synchronously shift the first portion of the first input state and the first portion of the first output state along the bus.
19. The computing system of claim 18 wherein the input-output system comprises a plurality of latches, the plurality of qubits coupleable to the bus via the plurality of latches, and the at least one processor causes the quantum processor to:
read the first output state from the plurality of qubits to the plurality of latches, and
read at least the first portion of the first output state from at least a first subset of the plurality of latches to the bus, the at least the first subset of the plurality of latches corresponding to the at least the first subset of the qubits.
20. The computing system of claim 19 wherein the at least one processor further causes the quantum processor to store at least a second portion of the first output state by the plurality of latches while the quantum processor transmits at least some of the first portion of the first output state along the bus.
21. The computing system of claim 20 wherein the at least one processor causes the quantum processor to set a first subset of the plurality of shift registers to latch and set a second subset of the plurality of shift registers to suppress to synchronously shift the first portion of the first input state and the first portion of the first output state along the bus.
22. The computing system of claim 21 wherein the at least one processor further causes the quantum processor to set a first latched shift register to latch, the first latched shift register neighboring a first holding shift register in a first direction, and set a first suppressed shift register to suppress, the first suppressed shift register neighboring the first holding shift register in a second direction opposing the first direction, the first holding shift register holding a unit of the first portion of the first input state.
23. The computing system of claim 22 wherein the at least one processor further causes the quantum processor to set a second latched shift register to latch, the second latched shift register neighboring a second holding shift register in the first direction, and set a second suppressed shift register to suppress, the second suppressed shift register neighboring the second holding shift register in the second direction opposing the first direction, the second holding shift register holding a unit of the first portion of the first output state.
24. The computing system of claim 23 wherein the at least one processor further causes the quantum processor to shift the first portion of the first input state and the first portion of the first output in the first direction.
25. The computing system of claim 14 , wherein the at least one processor further causes the quantum processor to:
read at least a first portion of the second output state from at least the first subset of the qubits to the bus;
transmit the first portion of the second output state along the bus to the output destination;
synchronously with transmitting the first portion of the second output state, transmit at least a first portion of a second input state along the bus from the input source;
write the first portion of the second input state to the first subset of the qubits; and
execute the problem and thereby generating a third output state based on the first portion of the second input state.
26. The computing system of claim 14 , wherein the at least one processor further causes the quantum processor to discard at least a second portion of the first output state.
27. An input-output system for a quantum processor, the quantum processor comprising a plurality of qubits, the input-output system comprising:
an input interface and an output interface;
a bus connected between the input interface and the output interface; and
a plurality of latches, the bus being communicatively coupled to the plurality of qubits by the plurality of latches;
wherein the plurality of latches comprises a bus proximate latch, an intermediate latch, and a qubit proximate latch, the qubit proximate latch being coupled to the plurality of qubits, the intermediate latch being coupled to the qubit proximate latch and the bus proximate latch, and the bus proximate latch being coupled to the bus.
28. The input-output system of claim 27 , wherein the input interface and the output interface each comprise one of a frequency-multiplexed resonator, a frequency and sensitivity tunable resonator, and a digital to analog converter.
29. The input-output system of claim 28 , wherein the bus comprises a first plurality of shift registers arranged in series and wherein each latch of the plurality of latches comprises a second plurality of shift registers arranged in series.
30. The input-output system of claim 29 , wherein each shift register of the first and second plurality of shift registers comprises a quantum flux parametron.
31. The input-output system of claim 30 , wherein each quantum flux parametron is addressed by a flux bias line, and wherein each quantum flux parametron has a suppressed state wherein the flux bias line introduces zero flux and a latched state wherein the flux bias line introduces non-zero flux.
32. The input-output system of claim 31 , wherein each shift register of the first and second plurality of shift registers is controllable by at least one of: individually, as subsets of commonly-controlled shift registers, and in groups of shift registers that are in series.
33. The input-output system of claim 32 , wherein each shift register of the first and second plurality of shift registers is proximately coupled only to independently-controllable shift registers.