IP Library › Granted Patent US 12,475,400
Granted Patent B2
US 12,475,400 · App. 18/735,514 · Granted Nov 18, 2025

Input/output systems and methods for superconducting devices

Inventor: Kelly T.R. Boothby (Vancouver, CA)
Assignee: D-WAVE SYSTEMS INC.
G06N10/40H10N60/12H10N60/805
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Quick Facts
Patent No.
US 12,475,400
App. No.
18/735,514
Granted
Nov 18, 2025
Kind
B2
Abstract

A quantum processor comprises a plurality of tiles, the plurality of tiles arranged in a first grid, and where a first tile of the plurality of tiles comprises a number of qubits (e.g., superconducting qubits). The quantum processor further comprises a shift register comprising at least one shift register stage communicatively coupled to a frequency-multiplexed resonant (FMR) readout, a qubit readout device, a plurality of digital-to-analog converter (DAC) buffer stages, and a plurality of shift-register-loadable DACs arranged in a second grid. The quantum processor may further include a transmission line comprising at least one transmission line inductance, a superconducting resonator, and a coupling capacitance that communicatively couples the superconducting resonator to the transmission line. A digital processor may program at least one of the plurality of shift-register-loadable DACs. Programming the first tile may be performed in parallel with programming a second tile of the plurality of tiles.

Claims (38)

1 . A quantum processor comprising a plurality of tiles, the plurality of tiles arranged in a first grid, each tile of the plurality of tiles comprising:

a shift register comprising at least one shift register stage communicatively coupled to a frequency-multiplexed resonant (FMR) readout;

one or more qubits of a plurality of qubits of the quantum processor;

one or more qubit readout devices, wherein the one or more qubit devices are communicatively coupled to the shift register, and each one of the one or more qubit readout devices is communicatively coupled to a respective one of the one or more qubits;

a plurality of digital-to-analog converter (DAC) buffer stages communicatively coupled to the shift register;

a plurality of shift-register-loadable DACs arranged in a second grid, wherein each one of the shift-register-loadable DACs is communicatively coupled to one of the plurality of DAC buffer stages; and

a plurality of control structures, wherein each control structure is operable to control a respective tile of the plurality of tiles, and a subset of the plurality of control structures share analog lines that are identically coupled to at least one of: respective pluralities of shift register stages and respective pluralities of shift-register-loadable DACs of correspondingly coupled tiles such that the subset of the plurality of control structures are operable to perform parallel input/output (I/O) operations among a subset of the plurality of tiles that comprises the correspondingly coupled tiles.

2 . The quantum processor of claim 1 wherein the plurality of qubits comprises a plurality of superconducting flux qubits.

3 . The quantum processor of claim 1 , further comprising a plurality of microwave transmission lines, wherein a respective FMR readout of each tile of the plurality of tiles is communicatively coupled to one of the plurality of microwave transmission lines.

4 . The quantum processor of claim 3 , wherein each microwave transmission line of the plurality of microwave transmission lines are communicatively coupled to one another.

5 . The quantum processor of claim 1 , wherein the FMR readout comprises a superconducting resonator.

6 . The quantum processor of claim 1 , wherein the first grid and the second grid are interspersed with each other on a superconducting integrated circuit.

7 . The quantum processor of claim 1 , further comprising:

one or more transmission lines, wherein a respective FMR readout of each tile of the plurality of tiles is communicatively coupled to one of the one or more transmission line, each of the one or more transmission lines comprising at least one transmission line inductance;

one or more superconducting resonators; and

one or more coupling capacitances that each communicatively couple one of the one or more superconducting resonators to a respective one of the one or more transmission lines.

8 . The quantum processor of claim 1 , wherein the FMR readout is communicatively coupled to at least one other element of the quantum processor by at least one of: a superconducting via, a bump bond, and a solder bond.

9 . The quantum processor of claim 1 , wherein the one or more qubits within each tile of the quantum processor includes a set of vertically-aligned qubits and a set of horizontally-aligned qubits, and each tile of the plurality of tiles further comprises:

a first communication street, the first communication street communicatively coupling the shift register to a subset of the one or more qubit readout devices that are communicatively coupled to the set of vertically-aligned qubits; and,

a second communication street, the second communication street communicatively coupling the shift register to a subset of the one or more qubit readout devices that are communicatively coupled to the set of horizontally-aligned qubits.

10 . The quantum processor of claim 9 , wherein each tile of the plurality of tiles further comprises:

a third communication street that communicatively couples the shift register to the plurality of DAC buffer stages; and,

a tee stage that communicatively couples the shift register to the third communication street and at least one of the first and second communication streets.

11 . The quantum processor of claim 10 , wherein:

each of the first, the second, and the third communication streets comprise a first, a second, and a third set of interleaved street stages; and,

wherein the analog lines of the plurality of control structures further comprise: a first, a second, and a third street stage global control line to respectively control transmission of data along the first, the second, and the third set of interleaved street stages,

wherein a first, a second, and a third street stage global annealing lines are shared among the first, the second, and the third communication streets within each tile and between tiles of the plurality of tiles.

12 . The quantum processor of claim 10 , wherein at least one of the first, the second, and the third communication streets each comprise a plurality of superconducting stages, and each superconducting stage of the plurality of superconducting stages and each shift register stage of the shift register comprises a quantum flux parametron (QFP).

13 . A method of programming a hybrid computing system, the hybrid computing system comprising a quantum processor and a digital processor, the quantum processor comprising a plurality of tiles, the plurality of tiles arranged in a first grid, each tile of the plurality of tiles comprising a shift register comprising a plurality of shift register stages communicatively coupled to a frequency-multiplexed resonant (FMR) readout, one or more qubits of a plurality of qubits of the quantum processor, one or more qubit readout devices communicatively coupled to the shift register, wherein each one of the one or more qubit readout devices is communicatively coupled to a respective one of the one or more qubits, a plurality of digital-to-analog converter (DAC) buffer stages communicatively coupled to the shift register, and a plurality of shift-register-loadable DACs arranged in a second grid, wherein each of the plurality of shift-register-loadable DACs is communicatively coupled to one of the plurality of DAC buffer stages, the quantum processor further comprising a plurality of control structures, wherein each control structure is operable to control a respective tile of the plurality of tiles, and a subset of the plurality of control structures share analog lines that are identically coupled to at least one of: respective pluralities of shift register stages and respective pluralities of shift-register-loadable DACs of correspondingly coupled tiles such that the subset of the plurality of control structures are operable to perform parallel input/output (I/O) operations among a subset of the plurality of tiles that comprises the correspondingly coupled tiles, the method comprising:

programming the quantum processor by the digital processor, and

reading out the quantum processor by the digital processor.

14 . The method of claim 13 , wherein the programming the quantum processor by the digital processor comprises: programming a first tile of the plurality of tiles, wherein the programming the first tile comprises programming at least one of the plurality of shift-register-loadable DACs.

15 . The method of claim 13 , wherein the programming the quantum processor by the digital processor further comprises: programming a first tile and a second tile of the plurality of tiles, wherein the programming the first tile of the plurality of tiles has a first duration and the programming the second tile of the plurality of tiles has a second duration, the first duration being at least approximately the same as the second duration.

16 . The method of claim 13 , wherein the programming the quantum processor by the digital processor further comprises: programming a first tile and a second tile of the plurality of tiles in parallel.

17 . The method of claim 13 , wherein the reading out the quantum processor by the digital processor comprises: reading out a first qubit of a first tile of the plurality of tiles in parallel with a second qubit of the first tile of the plurality of tiles.

18 . The method of claim 13 , wherein the reading out the quantum processor by the digital processor comprises: reading out a first qubit of a first tile of the plurality of tiles in parallel with a third qubit of a second tile of the plurality of tiles.

19 . The method of claim 13 , wherein the reading out the quantum processor by the digital processor comprises: reading out a first qubit of a first tile of the plurality of tiles and reading out a second qubit of a second tile of the plurality of tiles, wherein a first time taken to read out the first qubit of the first tile of the plurality of tiles is at least approximately the same as a second time taken to read out the second qubit of the second tile of the plurality of tiles.

20 . The method of claim 13 , further comprising calibrating, in parallel operations, at least a first portion of the quantum processor and a second portion of the quantum processor, the first portion of the quantum processor being non-local to the second portion of the quantum processor.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 12, 2025
From: BOOTHBY, KELLY T. R.
To: D-WAVE SYSTEMS INC.
Reel/Frame 072236/0122 →
CHANGE OF NAME Recorded Sep 12, 2025
From: DWSI HOLDINGS INC.
To: D-WAVE SYSTEMS INC.
Reel/Frame 072236/0400 →
MERGER Recorded Sep 12, 2025
From: D-WAVE SYSTEMS INC.; DWSI HOLDINGS INC.
To: DWSI HOLDINGS INC.
Reel/Frame 072881/0134 →
CONTINUATION Recorded Sep 12, 2025
From: D-WAVE SYSTEMS INC.
To: D-WAVE SYSTEMS INC.
Reel/Frame 072881/0928 →
Continuity (3)
Continuation 17607278
Provisional Application 62860098 · Jun 11, 2019
Related Publication 20240403684A1 · Dec 5, 2024
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