Layout techniques and optimization for power transistors
Various embodiments are disclosed for improved and structurally optimized transistors, such as RF power amplifier transistors. A transistor may include a drain metal portion raised from a surface of a substrate, a drain metal having a notched region, a gate manifold body with angled gate tabs extending from the gate manifold, and/or a source-connected shielding. The transistor may include a high-electron-mobility transistor (HEMT), a gallium nitride (GaN)-on-silicon transistor, a GaN-on-silicon-carbide transistor, or other type of transistor.
1. A field effect transistor, comprising:
a first source metal;
a second source metal;
a gate manifold comprising a gate manifold body, a first angled gate tab, and a second angled gate tab; and
a drain metal positioned between the first source metal and the second source metal over a channel of the field effect transistor, wherein the drain metal comprises a drain metal body having a notched region between the first source metal and the second source metal over the channel, the notched region defining a first projecting portion and a second projecting portion of the drain metal body, the first projecting portion and the second projecting portion positioned on respective sides of the notched region.
2. The field effect transistor of claim 1 , wherein the notched region is a triangular-shaped notched region.
3. The field effect transistor of claim 1 , wherein the notched region is a U-shaped notched region.
4. The field effect transistor of claim 1 , further comprising:
a substrate; and
a first drain metal column and a second drain metal column positioned below the drain metal, wherein:
an aperture is defined between the first drain metal column and the second drain metal column over the substrate and below the drain metal.
5. The field effect transistor of claim 1 , further comprising:
a first source-connected field plate (SFP), a second source-connected field plate (SFP), a first gate finger, and a second gate finger.
6. The field effect transistor of claim 1 , wherein the field effect transistor is a high-electron-mobility transistor (HEMT), a pseudomorphic high-electron mobility transistor (pHEMT), or a metamorphic high-electron mobility transistor (mHEMT).
7. The field effect transistor of claim 1 , wherein the field effect transistor is a gallium nitride (GaN)-on-silicon transistor or a GaN-on-silicon-carbide transistor.
8. A field effect transistor, comprising:
a first source metal;
a second source metal;
a gate manifold comprising a gate manifold body, a first angled gate tab extending to a first gate contact region at an end of the first source metal, and a second angled gate tab extending to a second gate contact region at an end of the second source metal; and
a drain metal, a first drain metal contact, and a second drain metal contact, the first drain metal contact and the second drain metal contact being positioned below the drain metal with an aperture between the first drain metal contact and the second drain metal contact below the drain metal, wherein:
the first angled gate tab extends at a first angle from the gate manifold body; and
the second angled gate tab extends at a second angle from the gate manifold body.
9. The field effect transistor of claim 8 , wherein:
the first angled gate tab comprises a first region extending from a first corner of the gate manifold body and a second region extending from the first region of the first angled gate tab to the first gate contact region;
the second angled gate tab comprises a first region extending from a second corner of the gate manifold body and a second region extending from the first region of the second angled gate tab to the second gate contact region; and
the first gate contact region and the second gate contact region are positioned wider apart from each other than a width of the drain metal positioned between the first source metal and the second source metal.
10. The field effect transistor of claim 9 , wherein:
the second region of the first angled gate tab is positioned parallel to and offset from a first side of the gate manifold body; and
the second region of the second angled gate tab is positioned parallel to and offset from a second side of the gate manifold body.
11. The field effect transistor of claim 8 , further comprising:
a first drain metal column and a second drain metal column positioned below the drain metal.
12. The field effect transistor of claim 11 , wherein:
the field effect transistor further comprises a substrate; and
the aperture is defined between the first drain metal column and the second drain metal column over the substrate and below the drain metal.
13. The field effect transistor of claim 8 , further comprising:
a first source-connected field plate (SFP), a second source-connected field plate (SFP), a first gate finger, and a second gate finger, wherein:
the first source metal and SFP and the second source metal and SFP are each sized and positioned to include an overhang that defines an overhang aperture in which the gate fingers are positioned, respectively.
14. The field effect transistor of claim 8 , wherein the field effect transistor is a high-electron-mobility transistor (HEMT), a pseudomorphic high-electron mobility transistor (pHEMT), or a metamorphic high-electron mobility transistor (mHEMT).
15. A field effect transistor, comprising:
a gate manifold, a first source metal, and a second source metal, the gate manifold comprising a gate manifold body, a first angled gate tab, and a second angled gate tab;
a drain metal positioned between the first source metal and the second source metal; and
a shielding having a first end connected to an end of the first source metal and a second end connected to an end of the second source metal, the shielding comprising a depressed region directly contacting a substrate, the depressed region extending along an end of the drain metal and between the end of the drain metal and the first and second angled gate tabs of the gate manifold.
16. The field effect transistor of claim 15 , wherein a width of the shielding is between 10 μm and 15 μm.
17. The field effect transistor of claim 15 , wherein the shielding comprises a first stepped region, a second stepped region, and the depressed region positioned between the first stepped region and the second stepped region, the depressed region directly contacting the substrate, the first stepped region and the second stepped region being raised from a surface of the substrate.
18. The field effect transistor of claim 17 , wherein:
the first angled gate tab extends through a recess defined by the first stepped region of the shielding such that the shielding does not contact the first angled gate tab; and
the second angled gate tab extends through a recess defined by the second stepped region of the shielding such that the shielding does not contact the second angled gate tab.
19. The field effect transistor of claim 15 , further comprising:
a substrate; and
a first drain metal column and a second drain metal column positioned below the substrate, wherein:
an aperture is defined between the first drain metal column and the second drain metal column over the substrate and below the drain metal.
20. The field effect transistor of claim 15 , further comprising:
a first source-connected field plate (SFP), a second source-connected field plate (SFP), a first gate finger, and a second gate finger, wherein:
the first SFP and the second SFP are each sized and positioned to include an overhang that defines an overhang aperture in which the gate fingers are positioned, respectively.