Second-order clock recovery using three feedback paths
An illustrative digital communications receiver and a fractional-N phase lock loop based clock recovery method provide substantially reduced sensitivity to nonlinearities in any included phase interpolators. One receiver embodiment includes: a fractional-N phase lock loop that provides a clock signal; a phase interpolator that applies a controllable phase shift to the clock signal to provide a sampling signal; a sampling element that produces a digital receive signal by sampling an analog receive signal; a timing error estimator that produces a timing error signal; a first feedback path coupling the timing error signal to the phase interpolator to minimize a phase component of the estimated timing error; a second feedback path coupling the timing error signal to the phase interpolator; and a third feedback path coupling the timing error signal to the fractional-N phase lock loop, the second and third feedback paths minimizing a frequency offset component of the estimated timing error.
1. An integrated receiver circuit that comprises:
a fractional-N phase lock loop that provides a clock signal;
a phase interpolator that applies a controllable phase shift to the clock signal to provide a sampling signal;
a sampling element that produces a digital receive signal by sampling an analog receive signal in accordance with the sampling signal;
a timing error estimator that produces a timing error signal indicating an estimated timing error of the sampling signal relative to the analog receive signal;
at least one feedback path coupling the timing error signal to the phase interpolator, the at least one feedback path using a phase error accumulator to minimize a phase component of the estimated timing error and using a frequency error accumulator to minimize a frequency offset component of the estimated timing error;
and
an additional feedback path coupling the timing error signal to the fractional-N phase lock loop to minimize the frequency offset component of the estimated timing error in parallel with said at least one feedback path.
2. The integrated receiver circuit of claim 1 , further comprising a demodulator that extracts a transmitted symbol stream from the digital receive signal.
3. The integrated receiver circuit of claim 1 , wherein the additional feedback path includes a division-ratio error accumulator.
4. The integrated receiver circuit of claim 3 , wherein as compared between short-term and long-term variation of the frequency offset component, the frequency error accumulator preferentially responds to short-term variation and the division-ratio error accumulator preferentially responds to long-term variation.
5. The integrated receiver circuit of claim 4 , wherein the frequency error accumulator comprises a leaky integrator and the division-ratio accumulator comprises an integrator with no leakage.
6. The integrated receiver circuit of claim 5 , wherein the at least one feedback path has a programmable phase error scaling coefficient K P , a programmable frequency error scaling coefficient K F , and a programmable leakage coefficient K L , and the additional feedback path has a division-ratio error scaling coefficient K D .
7. The integrated receiver circuit of claim 1 , wherein the phase error accumulator accumulates a combination of the timing error signal with a frequency offset signal from the frequency error accumulator.
8. The integrated receiver circuit of claim 1 , wherein the phase error accumulator accumulates a scaled timing error signal and the at least one feedback path includes a second phase error accumulator that accumulates a frequency offset signal from the frequency error accumulator.
9. The integrated receiver circuit of claim 8 , wherein the frequency error accumulator operates at a clock frequency lower than a clock frequency used by the phase error accumulator that accumulates the scaled timing error signal.
10. A clock recovery method that comprises, in an integrated receiver circuit:
generating a clock signal using a fractional-N phase lock loop;
interpolating a phase of the clock signal with a phase interpolator to produce a sampling signal;
sampling an analog receive signal in accordance with the sampling signal to obtain a digital receive signal;
producing a timing error signal indicating an estimated timing error of the sampling signal relative to the analog receive signal;
coupling the timing error signal to the phase interpolator via a first feedback path to minimize a phase component of the estimated timing error;
coupling the timing error signal to the phase interpolator via a second feedback path to minimize a short-term frequency offset component of the estimated timing error; and
coupling the timing error signal to the fractional-N phase lock loop via a third feedback path to minimize a long-term frequency offset component of the estimated timing error.
11. The clock recovery method of claim 10 , further comprising demodulating the digital receive signal to extract a transmitted symbol stream.
12. The clock recovery method of claim 10 , wherein the second feedback path includes a frequency error accumulator and the third feedback path includes a division-ratio error accumulator.
13. The clock recovery method of claim 12 , wherein the frequency error accumulator comprises a leaky integrator and the division-ratio accumulator comprises an integrator with no leakage.
14. The clock recovery method of claim 13 , wherein the first feedback path has a programmable phase error scaling coefficient K P , the second feedback path has a programmable frequency error scaling coefficient K F and a programmable leakage coefficient K L , and the third feedback path has a division-ratio error scaling coefficient K D .