Memory system for activating redundancy memory cell and operating method thereof
A memory system includes a memory device including a memory cell array including a plurality of memory cell groups, and a controller for selectively activating or inactivating one of the memory cell groups.
1. A memory system comprising:
a memory device including:
a memory cell array including normal memory cells and redundancy memory cells suitable for replacing failed memory cells among the normal memory cells; and
a device controller for activating reserved memory cells and generating a first signal associated with the reserved memory cells; and
a memory controller for assigning an address to enable accessing of the reserved memory cells in response to the first signal.
2. The memory system of claim 1 , wherein the memory device further includes a fuse unit storing the address assigned to the reserved memory cells.
3. The memory system of claim 1 , wherein the memory device further includes a power management unit separately providing power to the normal memory cells and the redundancy memory cells.
4. The memory system of claim 3 , wherein the power management unit selectively provides power to the reserved memory cells according to whether the reserved memory cells are used.
5. The memory system of claim 1 , wherein the memory device further includes a switching device disposed between first region memory cells and second region memory cells in order to couple the second region memory cells to a sense amplifier or decouple the second region memory cells from the sense amplifier.
6. The memory system of claim 1 , wherein the memory cell array includes a normal memory cell area and a redundancy memory cell area, and the redundancy memory cell area have a replacement memory cell region and a reserved memory cell region.
7. The memory system of claim 6 , wherein the memory device further includes a register suitable for generating the first signal indicating existence of the reserved memory cell region.
8. The memory system of claim 6 , wherein the memory device further includes a controller suitable for assigning an address for accessing a reserved memory cell of the reserved memory cell region based on the first signal.
9. The memory system of claim 1 , wherein the memory controller suitable for control the memory device, when first memory cells are accessed more than a threshold access number, to move data stored in the first memory cells to the reserved memory cells and replace the first memory cells with the reserved memory cells.
10. The memory system of claim 9 , wherein the memory controller assigns an address associated with the first memory cells to the reserved memory cells.
11. The memory system of claim 6 , wherein the memory device further includes a power management unit separately providing power to the replacement memory cell region and the reserved memory cell region.
12. The memory system of claim 5 , wherein when the switching device is enabled, the first region memory cell has a first operation speed, and the second region memory cell has a second operation speed slower than the first operation speed.
13. The memory system of claim 12 , wherein when the switching device is disabled, a bit line loading associated with the second region memory cell is decreased, and the first region memory cell has a third operation speed faster than the first operation speed.
14. The memory system of claim 5 , wherein when the switching device is enabled, the memory device stores data in the second region memory cell.
15. The memory system of claim 14 , wherein when a piece of the data stored in the second region memory is used more often than a threshold number, the memory device moves the piece of the data to the first region memory cell, and when the piece of the data is requested, the memory device accesses the first region memory cell and outputs the piece of the data.
16. The memory system of claim 5 , wherein when the switching device is enabled, the memory device operates as a normal mode, and when the switching device is disabled, the memory device operates as a fast mode faster than the normal mode.
17. The memory system of claim 5 , wherein the memory controller dynamically sets a mode of each of a plurality of memory devices, based on requests externally provided, by controlling a switching device of each of the plurality of memory devices.
18. The memory system of claim 1 , wherein the address is not assigned to access the normal memory cell.
19. The memory system of claim 6 , wherein the replacement memory cell region includes a plurality of replacement memory cells replaced with a plurality of failed memory cells included in the normal memory cell area, and the reserved memory cell region includes a plurality of reserved memory cells in a remaining region other than the replacement memory cell region.