High-voltage devices integrated on semiconductor-on-insulator substrate
View Patent ↗The present disclosure generally to semiconductor devices, and more particularly to semiconductor devices having high-voltage transistors integrated on a semiconductor-on-insulator substrate and methods of forming the same. The present disclosure provides a semiconductor device including a bulk substrate, a semiconductor layer above the bulk substrate, an insulating layer between the semiconductor layer and the bulk substrate, a source region and a drain region on the bulk substrate, a gate dielectric between the source region and the drain region, the gate dielectric having a first portion on the bulk substrate and a second portion on the semiconductor layer, and a gate electrode above the gate dielectric.
1. A semiconductor device comprising:
a bulk substrate;
a semiconductor layer above the bulk substrate;
an insulating layer between the semiconductor layer and the bulk substrate;
a source region and a drain region on the bulk substrate;
a gate dielectric between the source region and the drain region, the gate dielectric having a first portion on the bulk substrate and a second portion on the semiconductor layer;
a gate electrode above the gate dielectric;
a drift well in the bulk substrate; and
a drain extension region in the drift well, the drain extension region is located between the drain region and the gate electrode, wherein the insulating layer extends laterally to cover the drain extension region, and wherein the extended portion of the insulating layer covering the drain extension region is uncovered by the semiconductor layer.
2. The device of claim 1 , further comprising a body well in the bulk substrate, the body well is adjacent to the drift well, wherein the semiconductor layer and the insulating layer are positioned above the drift well.
3. The device of claim 2 , wherein the first portion of the gate dielectric is above the body well and the second portion of the gate dielectric is above the drift well.
4. The device of claim 2 , wherein the drain region is disposed upon an upper surface of the drift well.
5. The device of claim 2 , wherein the source region is disposed upon an upper surface of the body well.
6. The device of claim 2 , wherein the body well abuts the drift well.
7. The device of claim 2 , wherein the drift well and the drain region are of the same conductivity type.
8. The device of claim 2 , wherein the drift well and the body well have opposite conductivity types with respect to each other.
9. The device of claim 2 , wherein the bulk substrate comprises an isolation well located below the body well and the drift well.
10. A semiconductor device comprising:
a bulk substrate having an upper surface;
a semiconductor layer above the bulk substrate;
an insulating layer between the semiconductor layer and the bulk substrate;
a source region and a drain region on the bulk substrate, the source region and the drain region are raised above the upper surface of the bulk substrate;
a gate dielectric between the source region and the drain region, the gate dielectric having a first portion on the bulk substrate and a second portion on the semiconductor layer;
a gate electrode above the gate dielectric;
a body well and an adjacent drift well in the bulk substrate, wherein the semiconductor layer and the insulating layer are positioned above the drift well;
a drain extension region in the drift well, the drain extension region is located between the drain region and the gate electrode, wherein the insulating layer extends laterally to cover the drain extension region, and wherein the extended portion of the insulating layer covering the drain extension region is uncovered by the semiconductor layer.