Pattern fidelity enhancement with directional patterning technology
A method for semiconductor manufacturing includes providing a substrate, forming a patterning layer over the substrate, and patterning the patterning layer to form a hole in the patterning layer. The method also includes applying a first directional etching to two inner sidewalls of the hole to expand the hole along a first direction and applying a second directional etching to another two inner sidewalls of the hole to expand the hole along a second direction that is different from the first direction.
1. A method for semiconductor manufacturing, comprising:
providing a substrate;
forming a patterning layer over the substrate;
patterning the patterning layer to form a hole in the patterning layer;
applying a first directional etching to two inner sidewalls of the hole to expand the hole along a first direction; and
applying a second directional etching to another two inner sidewalls of the hole to expand the hole along a second direction that is different from the first direction.
2. The method of claim 1 , wherein the patterning of the patterning layer includes an extreme ultraviolet (EUV) lithography process.
3. The method of claim 1 , wherein each of the first and second directional etching includes a plasma etching process.
4. The method of claim 3 , wherein the plasma etching process is a slanted plasma etching process.
5. The method of claim 1 , wherein the first and second directions are perpendicular.
6. The method of claim 1 , wherein the first and second directional etching are applied simultaneously.
7. The method of claim 1 , wherein the first and second directional etching are applied sequentially.
8. The method of claim 1 , wherein the hole has rounded corners prior to the applying of the first and second directional etching, and wherein the rounded corners are converted to right-angle corners after the applying of the first and second directional etching.
9. A method for semiconductor manufacturing, comprising:
providing a substrate;
forming a resist layer over the substrate;
applying a first exposure to at least a first elongated region of the resist layer with a first exposure dosage below an exposure threshold of the resist layer;
applying a second exposure to at least a second elongated region of the resist layer with a second exposure dosage below the exposure threshold of the resist layer, wherein the first and second elongated regions overlap in a common region, wherein the second exposure dosage has a strength larger than that of the first exposure dosage in an edge portion of the common region; and
developing the resist layer to form a resist pattern corresponding to the common region.
10. The method of claim 9 , wherein in the common region a sum of the first and second exposure dosages is not lower than the exposure threshold of the resist layer.
11. The method of claim 9 , wherein each of the first and second elongated regions have rounded corners, and wherein the common region has a rectangular pattern with right-angle corners.
12. The method of claim 9 , wherein each of the first and second elongated regions has a L-shape.
13. The method of claim 12 , wherein the common region has two rectangular patterns with right-angle corners.
14. The method of claim 9 , wherein each of the at least the first and second elongated regions includes two parallel rectangular regions.
15. The method of claim 14 , wherein the common region has four rectangular patterns with right-angle corners.
16. The method of claim 14 , wherein the first and second exposure dosages have substantially a same peak strength.
17. A method for semiconductor manufacturing, comprising:
providing a substrate;
forming a resist layer over the substrate;
applying a first exposure to a first portion of the resist layer with a first exposure energy higher than an exposure threshold of the resist layer, wherein the first portion surrounds a first region;
applying a second exposure to a second portion of the resist layer with a second exposure energy higher than the exposure threshold of the resist layer, wherein the second portion has a second region overlapped with the first region; and
developing the resist layer to form a resist pattern corresponding to the first region minus the second region.
18. The method of claim 17 , wherein the second region has at least a right-angle corner extending into the first region.
19. The method of claim 17 , wherein the second region has two right-angle corners extending into the first region.
20. The method of claim 17 , wherein the resist pattern has a T-shape or a Z-shape.