Method and apparatus for dual multiplication units in a data path

1. A processor comprising:

a first data path and a second data path, wherein the first data path is a scalar data path and the second data path is a vector data path;

a first multiplication unit in the first data path of the processor, the first multiplication unit configured to perform single issue multiply instructions of a first set of instructions, wherein each of the single issue multiply instructions of the first set of instructions includes a respective first field indicating single issue multiply;

a second multiplication unit in the first data path, the second multiplication unit configured to perform single issue multiply instructions of a second set of instructions, wherein each of the single issue multiply instructions of the second set of instructions includes a respective second field indicating single issue multiply;

a third multiplication unit in the second data path of the processor, the third multiplication unit configured to perform single issue vector multiply instructions of a third set of instructions; and

a fourth multiplication unit in the vector data path, the fourth multiplication unit configured to perform single issue vector multiply instructions of a fourth set of instructions;

wherein the first multiplication unit and the second multiplication unit are configured to execute respective single issue multiply instructions in parallel;

wherein the third multiplication unit and the fourth multiplication unit are configured to execute respective single issue vector multiply instructions in parallel; and

wherein the third multiplication unit is further configured to perform single issue vector arithmetic instructions and to execute a single issue vector arithmetic instruction in parallel with execution of a single issue vector multiply instruction by the fourth multiplication unit.

2. The processor of claim 1 , wherein the single issue multiply instructions are scalar multiply instructions.

3. The processor of claim 1 , wherein the single issue multiply instructions of the third set of instructions are vector multiply instructions.

4. The processor of claim 1 , wherein the first multiplication unit is further configured to perform single issue arithmetic instructions, and wherein the first multiplication unit is further configured to execute a single issue arithmetic instruction in parallel with execution of a single issue multiply instruction by the second multiplication unit.

5. The processor of claim 1 , wherein the first multiplication unit and the second multiplication unit are further configured to operate together to execute a dual issue multiply instruction.

6. The processor of claim 1 , wherein the processor is a digital signal processor (DSP).

7. A method comprising:

decoding, by a processor, a first instruction having a first field indicating the first instruction is a first single issue multiply instruction;

decoding, by the processor, a second instruction having a second field indicating the second instruction is a second single issue multiply instruction;

decoding, by the processor, an arithmetic instruction and a third single issue multiply instruction;

executing the first single issue multiply instruction by a first multiplication unit in a first data path of the processor;

executing the arithmetic instruction by the first multiplication unit;

executing the second single issue multiply instruction by a second multiplication unit in the first data path, wherein the first single issue multiply instruction and the second single issue multiply instruction are executed in parallel;

executing the third single issue multiply instruction by the second multiplication unit, wherein the arithmetic instruction and the third single issue multiply instruction are executed in parallel;

storing, by the processor, a result of the first single issue multiply instruction in a storage location indicated by the first single issue multiply instruction and a result of the second single issue multiply instruction in a storage location indicated by the second single issue multiply instruction; and

storing, by the processor, a result of the arithmetic instruction in a storage location indicated by the arithmetic instruction and a result of the third single issue multiply instruction in a storage location indicated by the third single issue multiply instruction.

8. The method of claim 7 , wherein the first data path is a scalar data path and the first and second single issue multiply instructions are scalar multiply instructions.

9. The method of claim 7 , wherein the first data path is a vector data path and the first and second single issue multiply instructions are vector multiply instructions.

10. The method of claim 7 , further comprising:

decoding, by a processor, a first single issue vector multiply instruction and a second single issue vector multiply instruction;

executing the first single issue vector multiply instruction by a third multiplication unit in a vector data path of the processor;

executing the second single issue vector multiply instruction by a fourth multiplication unit in the vector data path, wherein the first single issue vector multiply instruction and the second single issue vector multiply instruction are executed in parallel; and

storing, by the processor, a result of the first single issue vector multiply instruction in a storage location indicated by the first single issue vector multiply instruction and a result of the second single issue vector multiply instruction in a storage location indicated by the second single issue vector multiply instruction.

11. The method of claim 10 , further comprising:

decoding, by the processor, a vector arithmetic instruction and a third single issue vector multiply instruction;

executing the vector arithmetic instruction by the third multiplication unit;

executing the third single issue vector multiply instruction by the fourth multiplication unit, wherein the vector arithmetic instruction and the third single issue vector multiply instruction are executed in parallel; and

storing, by the processor, a result of the vector arithmetic instruction in a storage location indicated by the vector arithmetic instruction and a result of the third single issue vector multiply instruction in a storage location indicated by the third single issue vector multiply instruction.

12. The method of claim 10 , further comprising:

decoding, by the processor, a dual issue multiply instruction;

executing the dual issue multiply instruction, wherein the first multiplication unit and the second multiplication unit operate together to execute the dual issue multiply instruction; and

storing, by the processor, a result of the dual issue multiply instruction in a storage location indicated by the dual issue multiply instruction.