Semiconductor device and method

1. A method comprising:

forming a dummy dielectric over a plurality of semiconductor layers;

forming a dummy gate over the dummy dielectric;

depositing a gate spacer adjacent the dummy gate and the dummy dielectric;

recessing the dummy gate to form a recess exposing the gate spacer;

implanting an impurity in a first region of the gate spacer to increase an etch rate of the first region of the gate spacer, a second region of the gate spacer remaining unmodified by the implanting, the impurity being implanted in a non-directional manner;

removing the dummy dielectric, the first region of the gate spacer, and remaining portions of the dummy gate to expose the semiconductor layers in the recess;

patterning the semiconductor layers to form nano-structures; and

forming a gate structure in the recess, the gate structure wrapped around the nano-structures, the gate structure contacting the second region of the gate spacer.

2. The method of claim 1 , wherein implanting the impurity in the first region of the gate spacer comprises:

flowing a gas source comprising an impurity source precursor gas and a carrier gas over the semiconductor layers;

generating a plasma from the gas source, the plasma comprising impurity ions and impurity radicals; and

accelerating the impurity ions in the plasma towards the gate spacer in a non-directional manner.

3. The method of claim 2 , wherein the impurity is oxygen, and the impurity source precursor gas comprises oxygen gas.

4. The method of claim 2 , wherein the impurity is nitrogen, and the impurity source precursor gas comprises nitrogen gas.

5. The method of claim 2 , wherein the plasma is generated at a temperature in a range of 20° C. to 650° C., at a pressure in a range of 5 mTorr to 500 mTorr, and at a radio frequency (RF) power in a range of 30 to 4000 watts, and wherein accelerating the impurity ions comprises applying a direct current (DC) bias having a low voltage of zero and a high voltage of up to 100 V.

6. The method of claim 2 , wherein the plasma is generated at a temperature in a range of 20° C. to 650° C., at a pressure in a range of 5 mTorr to 500 mTorr, and at a radio frequency (RF) power in a range of 30 watts to 4000 watts, and wherein accelerating the impurity ions comprises applying a RF bias having a low power of zero and a high power of up to 100 watts.

7. The method of claim 2 , wherein the plasma has a plasma density in a range of 10 9 cm −3 to 10 12 cm −3 .

8. The method of claim 1 , wherein removing the dummy dielectric and the first region of the gate spacer comprises:

performing an anisotropic dry etch in the recess, the anisotropic dry etch etching the dummy dielectric and the first region of the gate spacer at a greater rate than the second region of the gate spacer.

9. The method of claim 8 , wherein the impurity is oxygen, the gate spacer comprises silicon oxycarbonitride, the anisotropic dry etch is performed with nitrogen trifluoride, ammonia, or hydrogen fluoride, and the anisotropic dry etch converts the first region of the gate spacer to ammonium fluorosilicate, silicon tetrafluoride, or water byproducts.

10. The method of claim 8 , wherein the impurity is nitrogen, the gate spacer comprises silicon oxycarbonitride, the anisotropic dry etch is performed with nitrogen trifluoride, ammonia, or hydrogen fluoride, and the anisotropic dry etch converts the first region of the gate spacer to ammonium fluorosilicate or silicon tetrafluoride byproducts.

11. The method of claim 1 , wherein after removing the dummy dielectric, the first region of the gate spacer, and the remaining portions of the dummy gate, the recess has an upper width and a lower width, the upper width being greater than the lower width, a ratio of the upper width to the lower width being in a range of 1.1 to 11.

12. The method of claim 1 , wherein recessing the dummy gate comprises performing a first anisotropic dry etch process with methane at a first bias, and wherein removing the remaining portions of the dummy gate comprises performing a second anisotropic dry etch process with methane at a second bias, the second bias being different from the first bias.

13. A method comprising:

forming a gate spacer on a sidewall of a dummy gate, the dummy gate disposed on a channel region of a substrate;

increasing an etch rate of an upper region of the gate spacer relative a first etching process by non-directionally implanting an impurity in the gate spacer, more of the impurity being implanted in the upper region of the gate spacer than in a lower region of the gate spacer;

removing the upper region of the gate spacer by etching the upper region of the gate spacer with the first etching process;

exposing the channel region by removing dummy gate; and

forming a gate structure on the channel region of the substrate.

14. The method of claim 13 , wherein non-directionally implanting the impurity in the gate spacer comprises oxidizing the gate spacer.

15. The method of claim 13 , wherein non-directionally implanting the impurity in the gate spacer comprises nitrating the gate spacer.

16. The method of claim 13 , wherein a portion of the dummy gate is removed by etching the dummy gate with the first etching process.

17. The method of claim 13 , wherein a portion of the dummy gate is removed by etching the dummy gate with a second etching process, the second etching process being different from the first etching process.

18. A method comprising:

forming a gate spacer on a sidewall of a dummy gate, the dummy gate disposed on a channel region of a substrate;

recessing the dummy gate to expose an upper region of the gate spacer, a lower region of the gate spacer remaining covered by the dummy gate, wherein recessing the dummy gate comprises performing a first etch process with a first etchant at a first bias;

implanting an impurity in the gate spacer to modify the gate spacer, the lower region of the gate spacer being less modified by the implanting than the upper region of the gate spacer;

removing the upper region of the gate spacer and remaining portions of the dummy gate to expose the channel region, wherein removing the remaining portions of the dummy gate comprises performing a second etch process with the first etchant at a second bias, the second bias being different from the first bias; and

forming a gate structure on the channel region.

19. The method of claim 18 , wherein the lower region of the gate spacer is unmodified by the implanting the impurity in the gate spacer.

20. The method of claim 18 , wherein the lower region of the gate spacer is modified by the implanting the impurity in the gate spacer.