Methods and apparatus to facilitate read-modify-write support in a coherent victim cache with parallel data paths
Methods, apparatus, systems and articles of manufacture are disclosed facilitate read-modify-write support in a coherent victim cache with parallel data paths. An example apparatus includes a random-access memory configured to be coupled to a central processing unit via a first interface and a second interface, the random-access memory configured to obtain a read request indicating a first address to read via a snoop interface, an address encoder coupled to the random-access memory, the address encoder to, when the random-access memory indicates a hit of the read request, generate a second address corresponding to a victim cache based on the first address, and a multiplexer coupled to the victim cache to transmit a response including data obtained from the second address of the victim cache.
1. An apparatus comprising:
a set of interfaces configured to couple to a central processing unit;
a snoop interface configured to couple to a cache memory system and configured to receive a read request that specifies a first address to read;
a random-access memory coupled to the set of interfaces and to the snoop interface;
comparison logic coupled to the random-access memory and to the snoop interface and configured to determine whether the read request is associated with a hit in a victim cache;
an address encoder coupled to the comparison logic, the address encoder configured to, when the comparison logic indicates the read request is associated with a hit, generate a second address corresponding to the victim cache based on the first address;
the victim cache coupled to the address encoder; and
a multiplexer coupled to the victim cache to transmit a response including data obtained from the second address of the victim cache.
2. The apparatus of claim 1 , wherein the read request is transmitted by a level two data cache.
3. The apparatus of claim 1 , wherein the multiplexer is configured to be coupled to a victim cache storage queue, the multiplexer to obtain input data from the victim cache storage queue indicating a value to be written to the second address.
4. The apparatus of claim 3 , wherein the multiplexer is configured to transmit the response including the input data from the victim cache storage queue.
5. The apparatus of claim 1 , wherein the random-access memory is a tag random access memory.
6. The apparatus of claim 1 , wherein the victim cache is a multi-bank memory.
7. The apparatus of claim 1 , wherein the set of interfaces includes a scalar interface and a vector interface.
8. The apparatus of claim 7 , wherein the scalar interface is a sixty-four-bit wide interface, the vector interface is a five hundred and twelve-bit wide interface.
9. A system comprising:
a first memory system;
a second memory system configured to obtain a snoop request from the first memory system, wherein the second memory system includes:
a victim cache;
a random-access memory;
comparison logic coupled to the random-access memory and configured to determine whether the snoop request is associated with a hit in the victim cache based on the random-access memory;
an address encoder coupled to the comparison logic and configured to, when the snoop request is associated with a hit, generate an address corresponding to the victim cache; and
logic coupled to the address encoder and configured to transmit a response to the first memory system including data obtained from the address of the victim cache.
10. The system of claim 9 , wherein the first memory system is a level two cache memory system and the second memory system is a level one cache memory system.
11. The system of claim 9 , wherein the second memory system includes a multiplexer and a victim cache storage queue coupled to the multiplexer, the multiplexer configured to obtain input data from the victim cache storage queue indicating a value to be written to the address of the victim cache in the second memory system.
12. The system of claim 11 , wherein the multiplexer is configured to transmit the response including the input data from the victim cache storage queue.
13. The system of claim 9 , wherein the second memory system is coupled to a controller via a scalar interface and a vector interface, and the second memory system is coupled to the first memory system via a snoop interface.
14. The system of claim 13 , wherein the scalar interface is a sixty-four-bit wide interface, the vector interface is a five hundred and twelve-bit wide interface.
15. The system of claim 13 , wherein the controller is a central processing unit.
16. A method comprising:
obtaining, by a random-access memory, a read request indicating a first address to read via a snoop interface;
when the read request is a hit, generating a second address corresponding to a victim cache based on the first address; and
generating a response including data obtained from the second address of the victim cache.
17. The method of claim 16 , further including transmitting the read request from a level two data cache.
18. The method of claim 16 , further including obtaining input data from a victim cache storage queue indicating a value to be written to the second address.
19. The method of claim 18 , further including transmitting the response including the input data from the victim cache storage queue.
20. The method of claim 16 , wherein the victim cache is a multi-bank memory.