Methods and apparatus to reduce bank pressure using aggressive write merging

1. A method comprising:

obtaining a first memory operation that specifies to store a first set of data in a cache storage;

processing the first memory operation using a store queue that includes a pipeline that includes a first pipe stage and a second pipe stage;

obtaining a second memory operation that specifies to store a second set of data in the cache storage;

comparing an output of the first pipe stage with an output of the second pipe stage; and

based on the comparing, determining whether to:

merge the first set of data and the second set of data to produce a merged set of data;

provide the merged set of data to the first pipe stage; and

store the merged set of data in the cache storage.

2. The method of claim 1 , further comprising merging the first memory operation and the second memory operation by cancelling a part of the first memory operation.

3. The method of claim 2 , wherein the part of the first memory operation includes bytes that the second memory operation is to write to.

4. The method of claim 2 , wherein the part is a first part, and wherein the merging of the first memory operation and the second memory operation includes maintaining a second part of the first memory operation.

5. A system comprising:

a central processing unit coupled in parallel to a first cache storage and a second cache storage; and

a store queue that includes:

a set of pipe stages that includes a first pipe stage and a second pipe stage;

a comparator coupled to the first pipe stage and the second pipe stage; and

a merging circuit coupled to the first pipe stage;

wherein the store queue is operable to:

receive a first memory operation from the central processing unit that specifies to store a first set of data in the first cache storage;

prior to storing the first set of data in the first cache storage, receive a second memory operation from the central processing unit that specifies to store a second set of data in the first cache storage;

wherein the comparator is operable to:

compare the first memory operation as provided by the first pipe stage with the second memory operation as provided by the second pipe stage; and

determine whether to cause the merging circuit to:

merge the first set of data with the second set of data to produce a merged set of data; and

provide the merged set of data to the first pipe stage; and

wherein the store queue is operable to store the merged set of data in the first cache storage.

6. The system of claim 5 , wherein the merging circuit is operable to merge the first memory operation and the second memory operation by cancelling a part of the first memory operation.

7. The system of claim 6 , wherein the part of the first memory operation are bytes that the second memory operation is to write to.

8. The system of claim 6 , wherein the part is a first part, and the merging circuit is operable to merge the first memory operation and the second memory operation by maintaining a second part of the first memory operation.

9. The system of claim 8 , wherein the second part of the first memory operation are bytes that the second memory operation is not to write to.

10. The system of claim 5 , wherein the first cache storage is a main cache storage and the second cache storage is a victim cache storage.

11. An apparatus comprising:

a cache storage;

a store queue that includes:

an arbitration circuit coupled to the cache storage; and

a pipeline that includes:

a set of latches coupled in series that includes a first latch and a second latch:

pipeline circuitry coupled between the first latch and the second latch;

a comparator coupled to the first latch and the second latch; and

a merging circuit coupled to the first latch and to the pipeline circuitry;

wherein the store queue is operable to:

receive a first memory operation that specifies to store a first set of data in the cache storage; and

receive a second memory operation that specifies to store a second set of data;

wherein the comparator is operable to:

compare the first memory operation as stored in the first latch with the second memory operation as stored in the second latch; and

based on the comparison of the first memory operation to the second memory operation, determine whether to cause the merging circuit to:

merge the first set of data with the second set of data to produce a merged set of data; and

provide the merged set of data to the pipeline circuitry; and

wherein the arbitration circuit is operable to cause the merged set of data to be stored in the cache storage.

12. The apparatus of claim 11 , wherein the merging circuit is operable to merge the first memory operation and the second memory operation by cancelling a part of the first memory operation.

13. The apparatus of claim 12 , wherein the part of the first memory operation are bytes that the second memory operation is to write to.

14. The apparatus of claim 12 , wherein the part is a first part, and the merging circuit is operable to merge the first memory operation and the second memory operation by maintaining a second part of the first memory operation.

15. The apparatus of claim 14 , wherein the second part of the first memory operation are bytes that the second memory operation is not to write to.

16. The apparatus of claim 1 further comprising

a main cache storage; and

a victim cache storage;

wherein the cache storage is one of: the main cache storage or the victim cache storage.

17. The apparatus of claim 11 , wherein the pipeline circuitry includes at least one of: an arithmetic unit, an atomic comparison circuit, or a read-modify-write circuit.