Pseudo-random way selection

1. A method, comprising:

receiving a first request to allocate a line in an N-way set associative cache;

in response to a cache coherence state of a way of a set associated with the first request indicating that a cache line stored in the way is invalid, allocating the way for the first request; and

in response to no ways in the set having a cache coherence state indicating that the cache line stored in the way is invalid:

creating a masked subset of ways in the set by masking any way having a cache coherence state indicating that another request is pending for the way;

randomly selecting one of the ways in the masked subset; and

allocating the selected way for the first request,

wherein the cache coherence state of the cache line includes one bit indicating:

based on the cache line not having been allocated, whether the other request is pending for the way; and

based on the cache line having been allocated, a state of the cache line rather than whether the other request is pending for the way.

2. The method of claim 1 , further comprising, in response to the masked subset being empty, servicing the first request without allocating a line in the cache.

3. The method of claim 2 , wherein servicing the first request without allocating a line in the cache further comprises converting the first request to a non-allocating request and sending the non-allocating request to a memory endpoint identified by the first request.

4. The method of claim 1 , wherein allocating the way for the first request further comprises updating the cache coherence state of the selected way to indicate that the first request is pending for the selected way and sending the first request to a memory endpoint identified by the first request.

5. A method comprising:

receiving a request, wherein:

a cache includes lines arranged in sets of ways; and

the request is associated with a first set of ways of the cache;

determining whether any way of the first set of ways has an invalid state; and

based on none of the first set of ways having the invalid state:

masking a first subset of the first set of ways having a pending state to determine a second subset of the first set of ways that do not have the pending state;

selecting, using a random number generator, a way of the second subset of the first set of ways; and

allocating the selected way of the second subset for the request,

wherein a coherence scheme of the cache includes one bit for each line of the cache that indicates:

based on a line not having been allocated, whether the line has a pending state; and

based on the line having been allocated, a state of the line rather than the pending state.

6. The method of claim 5 further comprising, based on the second subset of the first set of ways being empty, servicing the request without allocating a way of the cache to the request.

7. The method of claim 6 , wherein the servicing of the request without allocating includes:

converting the request from allocating to non-allocating; and

providing the request to a memory endpoint.

8. The method of claim 5 further comprising:

setting the allocated way to have the pending state;

requesting data associated with the request;

storing the data in the allocated way; and

thereafter setting the allocated way to have a state selected from a group consisting of: a shared state, an exclusive state, or a modified state.

9. The method of claim 5 further comprising determining whether the request is an allocating request, wherein the determining, the masking, the selecting of the way, and the allocating of the way are performed based on the request being an allocating request.

10. The method of claim 5 , wherein:

the cache is a level two (L2) cache; and

the method further comprises:

retrieving data associated with the request from a level three (L3) cache; and

storing the data associated with the request in the allocated way of the L2 cache.

11. A level two (L2) cache subsystem, comprising:

a random number generator;

an L2 cache that includes lines arranged in sets of ways;

an L2 tag memory configured to store a respective state for each of the lines of the L2 cache; and

an L2 controller coupled to the L2 cache and the L2 tag memory and configured to:

receive a data request, wherein the data request is associated with a first set of ways of the L2 cache;

determine, based on the L2 tag memory, whether any way of the first set of ways has an invalid state; and

based on none of the first set of ways having the invalid state:

mask a first subset of the first set of ways having a pending state to determine a second subset of the first set of ways that do not have the pending state;

select a way of the second subset of the first set of ways using the random number generator; and

allocate the selected way of the second subset for the memory request,

wherein the respective state for each of the lines of the L2 cache includes one bit indicating:

based on a line not having been allocated, whether the line has a pending state; and

based on the line having been allocated, a state of the line rather than the pending state.

12. The L2 cache subsystem of claim 11 , wherein the L2 controller is further configured to, based on a first way of the first set of ways having the invalid state, allocate the first way for the memory request.

13. The L2 cache subsystem of claim 11 , wherein the L2 controller is further configured to, based on the second subset of the first set of ways being empty, service the memory request without allocating a way of the L2 cache to the memory request.

14. The L2 cache subsystem of claim 13 , wherein the L2 controller is configured to service the memory request without allocating by:

converting the memory request from allocating to non-allocating; and

providing the memory request to a level three (L3) cache subsystem.

15. The L2 cache subsystem of claim 11 , wherein the L2 controller is further configured to:

set the allocated way to have the pending state;

request data associated with the memory request;

store the data in the allocated way; and

thereafter, set the allocated way to have a state selected from a group consisting of: a shared state, an exclusive state, or a modified state.

16. The L2 cache subsystem of claim 11 , wherein the L2 controller is further configured to:

determine whether the memory request is an allocating request; and

perform the determining, the masking, the selecting of the way, and the allocating of the way based on the memory request being an allocating request.