Aggressive write flush scheme for a victim cache

1. A caching system comprising:

a first sub-cache; and

a second sub-cache in parallel with the first sub-cache, wherein the second sub-cache includes:

a set of cache lines;

line type bits configured to store an indication that a corresponding cache line of the set of cache lines is configured to store write-miss data; and

an eviction controller configured to:

determine that a first cache line of the second sub-cache storing write-miss data is full; and

evict the write-miss data stored in the first cache line in response to determining that the first cache line is full.

2. The caching system of claim 1 , wherein the eviction controller is further configured to:

determine that a second cache line of the second sub-cache storing write-miss data is half full; and

evict the write-miss data stored in the second cache line in response to determining that the second cache line is half full.

3. The caching system of claim 2 , wherein the eviction controller is configured to determine that no cache line of the second sub-cache storing write-miss data is fully written before evicting the write-miss data stored in the second cache line in response to determining that the second cache line is half full.

4. The caching system of claim 2 ,

wherein the second sub-cache further comprises a byte enable memory configured to store byte enable logic associated with the stored write-miss data,

wherein the byte enable memory includes a first bit,

wherein a value of the first bit indicates whether the first cache line is full, and

wherein the eviction controller is configured to determine that the first cache line is full by at least reading the value of the first bit.

5. The caching system of claim 4 ,

wherein the byte enable memory includes a second bit, and

wherein a value of the second bit indicates whether the second cache line is half full, and

wherein the eviction controller is configured to determine that the second cache line is half full by at least reading the value of the second bit.

6. The caching system of claim 5 , wherein the first and second bits are determined based on the byte enable logic associated with the stored write-miss data.

7. The caching system of claim 6 , wherein the first and second bits are determined based on the byte enable logic each time write-miss data is stored in the second sub-cache.

8. A method for caching data, comprising:

receiving, by a caching system, a write memory request for a memory address;

determining, by a first sub-cache of the caching system, that the memory address is not cached in the first sub-cache;

determining, by a second sub-cache of the caching system, that the memory address is not cached in the second sub-cache;

responsive to determining that the memory address is not cached in the second sub-cache, storing data associated with the write memory request in a first cache line of the second sub-cache;

responsive to determining that the memory address is not cached in the second sub-cache, storing, in a line type bit of the second sub-cache, an indication that the stored data corresponds to a write-miss;

determining that the first cache line is full; and

evicting write-miss data stored in the first cache line in response to determining that the first cache line is full.

9. The method of claim 8 , further comprising:

determining that a second cache line of the second sub-cache storing write-miss data is half full; and

evicting the write-miss data stored in the second cache line in response to determining that the second cache line is half full.

10. The method of claim 9 , further comprising determining that no cache line of the second sub-cache storing write-miss data is fully written before evicting the write-miss data stored in the second cache line in response to determining that the second cache line is half full.

11. The method of claim 9 , further comprising storing a first bit in a byte enable memory of the second sub-cache,

wherein a value of the first bit indicates whether the first cache line is full, and

wherein determining that the first cache line is full by at least reading the value of the first bit.

12. The method of claim 11 , further comprising storing a second bit in the byte enable memory of the second sub-cache,

wherein a value of the second bit indicates whether the second cache line is half full, and

wherein determining that the second cache line is half full by at least reading the value of the second bit.

13. The method of claim 12 , wherein the first and second bits are determined based on the byte enable logic associated with the stored write-miss data.

14. The method of claim 13 , wherein the first and second bits are determined based on the byte enable logic each time write-miss data is stored in the second sub-cache.

15. A device comprising:

a processor;

a first sub-cache; and

a second sub-cache in parallel with the first sub-cache; wherein the second sub-cache includes:

a set of cache lines;

line type bits configured to store an indication that a corresponding cache line of the set of cache lines is configured to store write-miss data, and

an eviction controller configured to:

determine that a first cache line of the second sub-cache storing write-miss data is full; and

evict the write-miss data stored in the first cache line in response to determining that the first cache line is full.

16. The device of claim 15 , wherein the eviction controller is further configured to:

determine that a second cache line of the second sub-cache storing write-miss data is half full; and

evict the write-miss data stored in the second cache line in response to determining that the second cache line is half full.

17. The device of claim 16 , wherein the eviction controller is configured to determine that no cache line of the second sub-cache storing write-miss data is fully written before evicting the write-miss data stored in the second cache line in response to determining that the second cache line is half full.

18. The device of claim 16 ,

wherein the second sub-cache further comprises a byte enable memory configured to store byte enable logic associated with the stored write-miss data,

wherein the byte enable memory includes a first bit,

wherein a value of the first bit indicates whether the first cache line is full, and

wherein the eviction controller is configured to determine that the first cache line is full by at least reading the value of the first bit.

19. The device of claim 18 ,

wherein the byte enable memory includes a second bit,

wherein a value of the second bit indicates whether the second cache line is half full, and

wherein the eviction controller is configured to determine that the second cache line is half full by at least reading the value of the second bit.

20. The device of claim 19 , wherein the first and second bits are determined based on the byte enable logic associated with the stored write-miss data.